laserbeak43
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of course, the xilinx database is no help with these warnings.WARNINGar:288 - The signal clki_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:288 - The signal rst_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNINGhysDesignRules:367 - The signal <clki_IBUF> is incomplete. The signal
WARNINGhysDesignRules:367 - The signal <rst_IBUF> is incomplete. The signal
parameter myparam = 43'hxx
parameter myparam = 44'hxx
The guy, who suggested this seems to have serious problems with calculating larger numbers...I was told that i had to make the parameters that i'm using 44-bits to match the clock.
parameter halfSec = 25'd25000000;
Heh, how embarrassing. In my friend's defense he just saw the bit-width i had created for my count reg and suggested that i make the bit-widths match so that the concatenation works correctly in the state machines. If he hadn't been getting off from what was probably a long day of work, i'm sure he would've noticed the issue. I, on the other hand, should have taken that bit-width into consideration when I had first started this revamp projectFvM said:The guy, who suggested this seems to have serious problems with calculating larger numbers...I was told that i had to make the parameters that i'm using 44-bits to match the clock.
hmm oops. wow can't believe i've missed all of that. I think i've made them match, but again, I'm not sure if values are 0 based or not. i don't think so thoughFvM said:As a next point, state has a too small width, so the state machine can't work at all. Curiously you have 6 bit wide constants (0x2A the highest), an inappropriate 5'h2A notation (should be 6'h2A accordingly) and a 4 bit wide register reg [3:0].
.
reg [24:0] cnt;
parameter halfsec = 25'd25000000
hmmm us2 should have beenFvM said:Better, but still incorrect.
Your assigning 6 bits to a seven bit register LEDl[6:0], unfortunately all other fields on the left are shifted by one bit, so the state
machine is still non-operational. That's the price you pay for using this highly elegant concatenation construct for your state machine:
One bit wrong and everything mixed up.
The below parameter is also calculated incorrectly, I don't know why you are using hexadecimal notation instead of readable decimal?
parameter us2 = 25'h100000; //2ms
ms2 = 25'd100000
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <state> in unit <LCDInit> has a constant value of 000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<6>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<5>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<4>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<3>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <WE> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <RS> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <RDB> in unit <LCDInit> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<2>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<1>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<0>> in unit <LCDInit> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <CE> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
Synthesizing Unit <LCDInit>.
Related source file is "init.v".
Found 4-bit tristate buffer for signal <dbo>.
Found 25-bit down counter for signal <cnt>.
Found 1-bit register for signal <LEDl<7>>.
Summary:
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 4 Tristate(s).
Unit <LCDInit> synthesized.
First thing..."LEDl[7] <= rst;" is a bad coding style
Your code looks like this :
if(rst) begin {cnt, state} <= 0; LEDl[7] <= rst; end
else
if(|cnt) cnt <= cnt - 1;
else
begin
u r case statement logic
end
I really didnt understand why u have this logic "if(|cnt) cnt <= cnt - 1;"
I think u might have seen transition from state 6'h0 to 6'h1 and you would in that state for ever. You will now have cnt = halfSec which will have some defined value and this statement will always becomes true "if(|cnt) cnt <= cnt - 1;" because u have atealst one-bit active in that cnt signal, it will take a long to go down to zero. Once it becomes zero, u will see another state transition.
Is this waht u want or Did i miss any point??
I really didnt understand why u have this logic "if(|cnt) cnt <= cnt - 1;"
...
Is this waht u want or Did i miss any point??
You're operating the state machine now, but don't generate meaningful output because of the below line. It's tristate most of the time. As long as you don't attempt to read from the display, you can simply enable the data line permanently.Better, but still incorrect.
assign dbo = (state==4'hA)? RDB : 4'bZZZZ;
assign dbo = RDB;
well the LCD is compatible with an Hitachi HD44780U, as you could've guessedFinally, you should care, if you're performing a valid initialization sequence. I wasn't motivated to decode the sequence, I just saw, that it's not the recommended "Initializing by Instruction" 4-Bit sequence, that can be expected to work independant of a previous display hardware reset.
Well ISE has a simulator, but i don't know how to write testbenches. I guess it's something I should learn how to do, but to be honest, it's quite intimidating, since the code for a testbench is usually 4x longer than the actual design... I'm looking for an alternative, like hardware debugging or something.[/code]By the way, don't you have a simulator or hardware debugger tool with your Xilinx enviroment to trace the design operation yourself?
In this case, it's not more than supplying a clock and reset signal, maximum 10 lines of code, plus the instantiation of the DUT as a module.since the code for a testbench is usually 4x longer than the actual design
No, if you have reason to assume, that the present one is correct as well. As I said, the difference can be in requiring a previous hardware reset. This condition can be expected after power on, but e.g. not after reloading a design. Performing the classical Hitachi fail-safe reset sequence possibly can avoid problems in testing.Should i just use the Hitachi version?
SOUNDS easy enoughFvM said:In this case, it's not more than supplying a clock and reset signal, maximum 10 lines of code, plus the instantiation of the DUT as a module.since the code for a testbench is usually 4x longer than the actual design
Not sure i'm familiar with this method, if it's in the Hitachi data-sheet, I've seen it though. I'm thinking a counter that starts when the system powers on and counts for like 50?s to let the LCD reach full power then init there.FvM said:No, if you have reason to assume, that the present one is correct as well. As I said, the difference can be in requiring a previous hardware reset. This condition can be expected after power on, but e.g. not after reloading a design. Performing the classical Hitachi fail-safe reset sequence possibly can avoid problems in testing.Should i just use the Hitachi version?
well my board communicates with 4 bits but yeah an 8bit version would've been niceFvM said:As another remark, as a next step, you may want to design a state machine, that can execute complete 8-Bit writes without needing to cut them in individual steps.
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