verilog language synthax

please how can i write these instructions with verilog's syntax? D1, D2 and D3 are signals.

sum3 <= D1 + D3*(-3.6139e-004);
sum6 <= D1*(1.9821) + D2*(1.5040) + D3*(0.4131);

I guess Verilog is not for this, you should probably try verilogA or some other becasue these are absolute values and cannot be digitally recognised using Verilog

The previous answer is a little misleading - you can represent any value digitally, as long as you pick a way to represent it.

Is this for synthesis or simulation? In simulation, your code may work as-is, as long as you've defined your signals appropriately, though I couldn't say for sure since I never have any reason to write Verilog of this nature.

In synthesis, you will need to decide on a number representation (e.g. fixed point or floating point) and precision. The easiest solution is then to use the vendor's IP cores to perform multiplications. For example, Xilinx has both fixed point and floating point operator cores. These will not be inferred from code and must be instantiated manually, and may not be purely combinatorial, so you will need to adjust your code and perhaps your design too.

Generally,the number we get from ADC is an integer.I suggest that you change your signal into a complement of integer.
You can multiply the signal by 2^n and then change them into complement of integer(in Matlab). At last, you just need shift the result right by n bits.

---------- Post added at 10:57 ---------- Previous post was at 10:51 ----------

Generally,the number we get from ADC is an integer.I suggest that you change your signal into a complement of integer.
You can multiply the signal by 2^n and then change them into complement of integer(in Matlab). At last, you just need shift the result right by n bits.

hi joelby,

theses instructions for synthesis purpose. I don't understand your reply for this reason because i'am new in verilog programming can you please explain more and i read instructions in literature like this: "assign sum5=D2 + {D2[23],D2[23:1]};
assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
assign sum7=sum6[23:19] + 1'b1;" i don't understand signals between {}.

i don't understand signals between {}.

Click to expand...

That's saying "I'm new to Verilog" in other words. You should learn about the syntax. This is a concatenation operation, see chapter 4.1.14 in the Verilog specification, or a different one in your text book.

Regarding your original question, you need to define number formats for the involved quantities. I assume, they are unsigned or signed numbers, but bit widths must be specified, at least if th ecode is intended for synthesis. The real factors have to be represented by fractional numbers.