snfvsd
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The verilog netlist has this statement for instantiating fillers:
FILLERD1TD FILLER_323334();
FILLERC4TD FILLER_323334();
The cell FILLERD1TD has a symbol view only as its a pass through, but FILLERC4TD has a symbol and a schematic as it is has some moscaps. Both symbols do not have any pins as the power and grounds are globals in the CDL netlist. During verilog import the top is imported as a functional view as the symbol of the fillers is not used due to the following error:
VerilogIn: *W,156: Rejecting lib 'FSR0T_D_GENERIC_CORE_MLX' cell 'FILLERD1TD' view 'symbol' for module 'FILLERD1TD' because terminal does not exist for a port in portOrder property.
VerilogIn: *W,156: Rejecting lib 'FSR0T_D_GENERIC_CORE_MLX' cell 'FILLERC4TD' view 'symbol' for module 'FILLERC4TD' because terminal does not exist for a port in portOrder property.
Please let me know if you know a easy fix. I have tried to play around with the cell CDFs but it did not help.
FILLERD1TD FILLER_323334();
FILLERC4TD FILLER_323334();
The cell FILLERD1TD has a symbol view only as its a pass through, but FILLERC4TD has a symbol and a schematic as it is has some moscaps. Both symbols do not have any pins as the power and grounds are globals in the CDL netlist. During verilog import the top is imported as a functional view as the symbol of the fillers is not used due to the following error:
VerilogIn: *W,156: Rejecting lib 'FSR0T_D_GENERIC_CORE_MLX' cell 'FILLERD1TD' view 'symbol' for module 'FILLERD1TD' because terminal does not exist for a port in portOrder property.
VerilogIn: *W,156: Rejecting lib 'FSR0T_D_GENERIC_CORE_MLX' cell 'FILLERC4TD' view 'symbol' for module 'FILLERC4TD' because terminal does not exist for a port in portOrder property.
Please let me know if you know a easy fix. I have tried to play around with the cell CDFs but it did not help.