[verilog] How is a always@* block synthesized

pigtwo · Dec 16, 2016

Hello all,

I have a basic question about how a certain block is synthesized. Take for example the code below:

Code Verilog - [expand]
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module blah(input wire clk);
 
   reg state, state_next;
 
   always @(posedge clk)
   begin
      state <= state_next;
   end
 
   always@*
   begin
      state_next = state + 1;
   end
endmodule

I understand that the first always block will produce a register that is clocked by 'clk' but what does the second always block synthesize to? Does it just become pure combination logic(IE even though state_next is declared a reg it would really synthesize as a wire)?

For clarification I don't mean how is an incrementer synthesized(this is just an example) but more generally how registers in a always@* block are handled.

Thank you for the help!

ads-ee · Dec 16, 2016

A always @* block will never produce a flip-flop in a design it might produce a latch if there is feedback, otherwise you get a combinational blob.

The reg keyword does not by definition produce flip-flops it only means the signal will hold state until changed by an assignment. This is part of the reason for changing it to logic in SV. Wire on the otherhand is just that interconnection wires like you would put on a prototype board.

pigtwo · Dec 16, 2016

That makes perfect sense, thank you. I think it was just the terminology was confusing me.

[verilog] How is a always@* block synthesized

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12 13 14	module blah(input wire clk); reg state, state_next; always @(posedge clk) begin state <= state_next; end always@* begin state_next = state + 1; end endmodule

[verilog] How is a always@* block synthesized

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