[Verilog HDL] Verilog code for 8-bit ALU with clock gating technique?

[Siong Hui]

Good days. Can someone guide me on how to write Verilog code for 8-bit ALU with clock gating technique?

 

[KlausST]

Hi,

It starts with specifications, requirements, feature list...
Then you need some basic knowledge about hardware and HDL to be able to divide the "big task" into a couple of smaller tasks
Then take one (by one) of the smaller tasks and divide them into even smaller tasks.
Do this until you come to a point where every task is so small that it easily can be coded.
At this point you need some deeper knowledge about how to write verilog code.

Often forgotten:
Write the tiny snippets of code
* then test them
* and correct them if necessary
* write documentation

Combine some snippets .. then again test them ... do this until the whole code is finished.

We often see code, schematics, software... written all at once, but they don't work. And the member has no idea what's wrong, can't give no useful error description.

Mind:
* you do the job, you do the sketches, write code
* we help to rectify mistakes, and how to improve it.

Generally: Don't expect that members spend more time for the reply than you show. When you write a single line without details, you have to expect that the replies are also one line without details.
Show your effort, show what you have done, show your ideas, give links to documents..

Klaus

 

[Siong Hui]

Hi, thank you for your reply. Actually, I already do some research about this, but I still don't know how to write the coding. So, thank you again for your guidance.

 

[danadakk]

On youtube search for "Verilog", tons of training videos.

Go to FPGA websites, they also have training series.

Site Keyword Search

Keyword search for xilinx.com

www.xilinx.com

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Using Xilinx FPGA's

www.udemy.com

Regards, Dana.

 

[KlausST]

but I still don't know how to write the coding

so the real question is..
* How to divide into smaller tasks
* VERILOG semantic / coding
* ALU functions
* clock gating
????

Klaus

 

[ThisIsNotSam]

is this homework? because it is the only scenario where I can think of of someone asking you to write clock gating code.