[Verilog] function problem?

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davyzhu

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Hi all,

I want to use function to write small combinational logic.
But I found it seems I cannot declear wire in function,why?
Any suggestions will be appreciated!

The func_test have some compile error, why?
//--------func_test---------------
module func_test(
in_1,
in_2,
in_3,
out,
);

input [5:0] in_1;
input [5:0] in_2;
input [5:0] in_3;

output [5:0] out;

assign out = plus_out(in_1,in_2,in_3);

function [5:0] plus_out;
input [5:0]in_1;
input [5:0]in_2;
input [5:0]in_3;
wire [5:0] plus;
begin
plus = in_1+in_2;
plus_out = plus + in_3;
end
endfunction

endmodule

Best regards,
Davy
 

Hi,
In the function definition you have to use the same name for the o/p register as the function name itself. You have declared function name as plus_out and assigned o/p to "out". Change this and see if it works.

Also you have used assign inside a function definition. Do you think this is correct ?

Best Regards,
 

Here is the corrected code study this and see if you can get the
answers you are looking for!
Code: 
module func_test(
                 in_1,
                 in_2,
                 in_3,
                 out,
                 );
   
   input [5:0] in_1;
   input [5:0] in_2;
   input [5:0] in_3;
   
   output [5:0] out;

   function [5:0] plus_out;
      input [5:0]in_1;
      input [5:0]in_2;
      input [5:0]in_3;
      reg [5:0] plus;
      begin
         plus = in_1 + in_2;
         plus_out = plus + in_3;
      end
   endfunction 
   
   assign      out = plus_out(in_1,in_2,in_3);
   
endmodule // func_test
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Hi,

I changed wire to reg in function and all passed! Thanks!
But I am confused about that. For in my mind, reg is always used in 'always' block as sequential logic!
And in function there is only combinational logic, why?

Any suggestions will be appreciated!

Best regards,
Davy
 

Hi,
The functions are defines as procedural block only. Also the functions can be called from behavioral block only, so what it means. The functions are just like any behavioral block. Please refer to this link. It mentions clearly that wire can not be defined inside a function definition.
**broken link removed**

Funtions are useful to model combinational logic. Thats true, but this does not mean that defining a variable as reg will not model combinational logic.

Best Regards,
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
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