madushan
Newbie level 4
![Newbie level 4](/styles/images/ranks/blevel1.gif)
Hi,
I have a question regarding how verilog for loops work when synthesized
assume this code
reg [7 : 0] array = 2'b10101010;
reg found = 0;
integer j = 0;
integer i;
always @ (posedge clk) begin
for (i = 0; i < 8; i = i + 1) begin
if (array) begin
if (!found) begin
j <= i;
found <= 1'b1;
end
end
end
end
please consider the execution for only 1 clock cycle,
what will be the value of j after 1 clock cycle?
I think in the synthesized circuit, the value will be a garbage,
in the simulation the value of j will be 1
Did I get this correctly?
Please explain
Thanks
I have a question regarding how verilog for loops work when synthesized
assume this code
reg [7 : 0] array = 2'b10101010;
reg found = 0;
integer j = 0;
integer i;
always @ (posedge clk) begin
for (i = 0; i < 8; i = i + 1) begin
if (array) begin
if (!found) begin
j <= i;
found <= 1'b1;
end
end
end
end
please consider the execution for only 1 clock cycle,
what will be the value of j after 1 clock cycle?
I think in the synthesized circuit, the value will be a garbage,
in the simulation the value of j will be 1
Did I get this correctly?
Please explain
Thanks