Verilog examples of how to implement a master/slave SPI

[bb12mpc]

Master/Slave SPI

Is there any example or source verilog for how to implement a master/slave SPI? Thanks!

 

[liu_uestc]

Master/Slave SPI

i have write one but just have master mode ;because i don't need slave mode;give me some money i do for you !just a little .ok?

 

[o0vvv0o]

Re: Master/Slave SPI

it that SPI need Money ? We usually send it free in 8 bit mode

 

[RegUser_2]

Re: Master/Slave SPI

Is there any example or source verilog for how to implement a master/slave SPI? Thanks!

Here, enjoy

(And it's free. I believe that one who ask money for help should leave this forum)

 

[theHermes]

hey, I cant see the code now. can someone help me by reposting the code if possible.
thanks a lot!!