Verilog Error!!

[jeetesh]

I am getting an error as: ERROR:HDLCompilers:26 - "OAI21.v" line 26 expecting 'endmodule', found 'if'
21: module OAI21(a, b, cntrl, z);
22: input a, b, cntrl;
23: output z;
24: reg z;
25: always @(a or b or cntrl);
26: if (cntrl)
27: z = a & b;
28: else
29: z = a | b;
30: endmodule
Help me
Thanks in advance!!

 

[manikanta.mashetti]

Hie,

use begin....end in the always block ...

 

[naseer_39]

Hi,

Remove semicolon after always block sensitivity list and add begin and end.

Naseer