Verilog Error!! Please help me...

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jeetesh

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I am getting an error at the udp instantiation line, while viewing RTL schematic, as: Unsupported Switch or User Defined Primitive
but syntex is correct.... help me.. I am using xilinkx 14.1

Code Verilog - [expand]
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primitive udp (d,a,b,c);
    output d;
    input a,b,c;
    table
      //a b c   : d;
    0 0 0 : 0;
    0 0 1 : 1;
    0 1 0 : 1;
    0 1 1 : 0;
    1 0 0 : 1;
    1 0 1 : 0;
    1 1 0 : 0;
    1 1 1 : 1;
    endtable
endprimitive
 
module xor3_udp(x,y,u,v,w);
    input u,v,w;
    output x,y;
    and (y,u,v);
    udp (x,u,v,w);
 
endmodule
 
Last edited by a moderator:

while instantiating udp, you need to provide both udpname and udp instance name.
like, udp udp_inst(x,u,v,w);
you need to follow the same syntax as module instantiation.
 

It is again showing same error while viewing RTL Schematics.. @yourcheers
 

why do you used a primitive?
and not a custom module?
 

I don't think UDP is supported for synthesis in the Xilinx tools. It's for simulation only.
 

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