Verilog Error: expecting 'endmodule', found 'for'

Code Verilog - [expand]
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module approximateMultiplier(
    input [7:0] a,b,
    output [15:0] s
    );
 
    wire [15:0] p0, p1, p2, p3 ,p4 ,p5, p6, p7;
    wire [15:0] q0, q1, q2, q3;
    wire [15:0] r0, r1;
    wire [15:0] e1, e2, e3, e4, e5, e6, e7;
    wire [15:0] s_, e_, E;
    wire [4:0]c;
    
    supply0 zero;
    
    //generating the partial products p0-p7
    assign p0 = b[0]*a;
    
    assign p1 = b[1]*a;
    assign p1 = p1<<1;
    
    assign p2 = b[2]*a;
    assign p2 = p2<<2;
    
    assign p3 = b[3]*a;
    assign p3 = p3<<3;
    
    assign p4 = b[4]*a;
    assign p4 = p4<<4;
    
    assign p5 = b[5]*a;
    assign p5 = p5<<5;
    
    assign p6 = b[6]*a;
    assign p6 = p6<<6;
    
    assign p7 = b[7]*a;
    assign p7 = p7<<7;
    
    integer i;  //loop variable
    //Zero pad the remaining bits int the left side of p0-p7
    assign p0[15:8] = 8'b0000_0000;
    assign p1[15:9] = 7'b0000_000;
    assign p2[15:10] = 6'b0000_00;
    assign p3[15:11] = 5'b0000_0;
    assign p4[15:12] = 4'b0000;
    assign p5[15:13] = 3'b000;
    assign p6[15:14] = 2'b00;
    assign p7[15] = 1'b0;
    
    
    //Now we have p0-p7. Genarate q0-q3
    for(i=0; i<=8; i=i+1)                            //ERROR IN THIS LINE
    begin
        if(i==0)    //the 0-th bit will not have any (i-1)-th term. Hence, seperately calculated.
        begin
            //assigning the values to the 0-th bits of q0-q3
            assign q0[i] = p0[i]^p1[i];
            assign e1[0] = 0;
            
            assign q1[i] = 0;
            assign q1[i+1] = 0;
            assign q1[i+2] = p2[i+2]^p3[i+2];
            assign e2[i] = 0;
            assign e2[i+1] = 0;
            
            assign q2[i] = 0;
            assign q2[i+1] = 0;
            assign q2[i+2] = 0;
            assign q2[i+3] = 0;
            assign q2[i+4] = p4[i+4]^p5[i+4];
            assign e3[i] = 0;
            assign e3[i+1] = 0;
            assign e3[i+2] = 0;
            assign e3[i+3] = 0;
            
            assign q3[i] = 0;
            assign q3[i+1] = 0;
            assign q3[i+2] = 0;
            assign q3[i+3] = 0;
            assign q3[i+4] = 0;
            assign q3[i+5] = 0;
            assign q3[i+6] = p6[i+6]^p7[i+6];
            assign e4[0] = 0;
            assign e4[i+1] = 0;
            assign e4[i+2] = 0;
            assign e4[i+3] = 0;
            assign e4[i+4] = 0;
            assign e4[i+5] = 0;
            
            //assigning the values to the 0-th bits of r0 and r1
            assign r0[i] = q0[i]^q1[i];
            assign e5[0] = 0;
            
            assign r1[i] = 0;
            assign r1[i+1] = 0;
            assign r1[i+2] = 0;
            assign r1[i+3] = 0;
            assign r1[i+4] = q2[i+4]^q3[i+4];
            assign e6[i] = 0;
            assign e6[i+1] = 0;
            assign e6[i+2] = 0;
            assign e6[i+3] = 0;
            
            //assigning the values to the 0-th bits of s_
            assign s_[i] = r0[i]^r1[i];
            assign e7[0] = 0;
        end
        
        else    //fill other bits
        begin
            assign q0[i] = (p0[i]^p1[i]) | (p0[i-1] & p1[i-1]);
            assign e1[i] = (p0[i]^p1[i]) & p0[i-1] & p1[i-1];
            
            assign q1[i+2] = (p2[i+2]^p3[i+2]) | (p2[i+1] & p3[i+1]);
            assign e2[i+2] = (p2[i+2]^p3[i+2]) & p2[i+1] & p3[i+1];
            
            assign q2[i+4] = (p4[i+4]^p5[i+4]) | (p4[i+3] & p1[i+3]);
            assign e3[i+4] = (p4[i+4]^p5[i+4]) & p4[i+3] & p1[i+3];
            
            assign q3[i+6] = (p6[i+6]^p1[i+6]) | (p0[i+5] & p1[i+5]);
            assign e4[i+6] = (p6[i+6]^p1[i+6]) & (p0[i+5] & p1[i+5]);
        end
    end
    
    //Zero pad the remaining bits int the left side of q0-q3
    for(i=9; i<=15; i=i+1)
    begin
        assign q0[i] = 0;
        assign q1[i+2] = 0;
        assign q2[i+4] = 0;
        assign q3[i+6] = 0;
    end
    
    
    
    //Now we have q0-q3. Generate r0 and r1
    for(i=1; i<=10; i=i+1)
    begin
        assign r0[i] = (q0[i]^q1[i]) | (q0[i-1] & q1[i-1]);
        assign e5[i] = (q0[i]^q1[i]) & q0[i-1] & q1[i-1];
        
        assign r1[i+4] = (q2[i]^q3[i]) | (q2[i-1] & q3[i-1]);
        assign e6[i+4] = (q2[i]^q3[i]) & q2[i-1] & q3[i-1];
    end
    
    //Zero pad the remaining bits int the left side of r0 and r1
    for(i=11; i<=15; i=i+1)
    begin
        assign r0[i] = 0;
        assign r1[i+4] = 0;
    end
    
    
    
    //Now we have r0 and r1. Genarate s_
    for(i=1; i<=15; i=i+1)
    begin
        assign s_[i] = (r0[i]^r1[i]) | (r0[i-1] & r1[i-1]);
        assign e7[i] = (r0[i]^r1[i]) & r[i-1] & r1[i-1];
    end
    
    
    //Now we have s_. Accumlate e_ = e3|e4|e6|e7
    assign e_ = e3|e4|e6|e7;
    //mask all other bits of e_ and keep 11-14 alive only. Save this error part in E
    assign mask = 16'h7800;
    assign E = mask & e_;
    
    //we have s_ and accumulated error E. Add them to get the inaccurate result.
    assign s = s_;
    fullAdder F1(s_[11], E[11], zero, s[11], c[0]);
    fullAdder F2(s_[12], E[12], c[0], s[12], c[1]);
    fullAdder F3(s_[13], E[13], c[1], s[13], c[2]);
    fullAdder F4(s_[14], E[14], c[2], s[14], c[3]);
    fullAdder F5(s_[15], c[3], zero, s[15], c[4]);
endmodule

Code Verilog - [expand]
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// you wrote three assignments that won't actually work correctly
// based on your software implementation.
assign p1 = b[1]*a;
assign p1 = p1<<1;
assign p1[15:9] = 7'b0000_000;
 
// you should have written a single assignment like this:
assign p1 = {7'b0, b[1]*a, 1'b0};