verilog dynamic instantiation ??

[sivasankar]

Hi,
Does any body know How to replicate a module instantiation for multiple time dynamically in VERILOG?
example

`ifdef PHY_MEM_4
`define MEM 4
`elsif PHY_MEM_5
`define MEM 5
`endif


RAM U_RAM (
cs_n,
cas_n
ras_n,

.....);

I want this RAM instance to be replicated multiple times depending upon the compilier dirictives `define MEM 4 or 5 or 6...

reply me
sivasankar

 

[EEHardware]

i want to konw about this ,too.
can anyone konw, please reply and pm me!

 

[zhangyong]

Sorry, I think there is no simle/shortcut way

 

[silver_kiss]

there is no short cut u hve to write it but internal signals u hve choice to use or not

 

[radix]

Good time to switch to VHDL and use the generate statement.

Just kidding, so no flames or starting of a religious war between VHDL and verilog, okay?

I think what a lot of folks do is run a pre-processor, like a perl script, on their verilog code to handle things like this. I mainly use VHDL but I worked at a verilog shop a couple of years back where one of the guys would name his original source files *.vpre. Then he would run his pre processor on them and convert them to standard *.v files. In addition to replicating instantiations he would also do some rudimentary type/port width checking.

Radix