Verilog "Dash" operator

Hello,

What is the purpose of the # operator in Verilog?

I guess you are asking about Verilog delay specifications? # is a symbol here, it's no operator.

It's all in the LRM.

There is no such opertor in verilog.If you want to learn about operator follow the link below.
iroi.seu.edu.cn/books/asics/Verilog/LRM/HTML/04/ch04.1.htm
But in modeling delay it is used ie for controling the time.For example
x = #1 y;
We can also use it in trise,tfall,toff,min,typ and max values.

I guess you are asking about Verilog delay specifications?

Click to expand...

I'm asking about the # at the "module" declaration in page 4 of this document.
**broken link removed**

It's all in the LRM

Click to expand...

Is this the latest LRM?
http://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf

This # operator is used for assigning the values for parameter, just like generic declaration in VHDL.
If we are assigning values using the # operator during the instantiation then the value inside the module will be over assigned with the new value.

So...if the # isn't in place - parameters won't be assigned from the upper hierarchy ?

It's the syntax for the optional definition of module parameters and parameter value assignment in module instantiation.

Alternatively parameters can be defined in the module body and modified with defparam statements in the instantiation.

So, using the # allows us to avoid the use of "defparam" ?

As if the # "opens a lock" that allows the upper hierarchy to force its generics and overwrite the original one?

defparam is planned to be removed in future Verilog versions, using it with module instantiations means to throw away a specific language construct (module parameters) in this situation.

FvM said:

defparam is planned to be removed in future Verilog versions, using it with module instantiations means to throw away a specific language construct (module parameters) in this situation.

Click to expand...

One reason to not use defparam is a defparam can be placed anywhere in the code. You can place a defparam that changes a parameter in another module as long as you supply the full hierachical name to the parameter. You can also place the defparam anywhere in the module that the instantiates the module you are changing parameters.

Problems like having multiple defparams affecting the same parameter could be introduced, where compile order would become significant as the defparam would be redefined with the wrong value prior to parsing the file that uses the redefinition.

To sum up this thread, "#" is used in two different contexts: In a procedural context, it is used as a delay control to block execution of the current procedural thread, and in a structural context, it is used to declare or override a set of parameters.

Using the # allows you to override the parameter from above. If you do not provide an override, it uses the default value. SystemVerilog adds the ability to have no default, which forces the user to provide an override when instantiating a module instance. It also adds the ability to parameterize types as well as values.

It is unlikely the defparam statement will ever be removed; there is too much existing code out there using it. We been trying to get people to stop using it since 1990, but old habits are hard to remove. The reason this construct is bad is because it relies on hierarchical references to perform the override.

The latest version of the LRM can be found .

dave_59 said:

To sum up this thread, "#" is used in two different contexts: In a procedural context, it is used as a delay control to block execution of the current procedural thread, and in a structural context, it is used to declare or override a set of parameters.

Click to expand...

Concisely summarized.