Verilog construct for casex and casez

[sun_ray]

Can casex and casez statement have non binary case item?

 

[dave_59]

If by binary you mean integral value and non-binary you mean real; it is legal, though not very useful.

 

[yadavvlsi]

You can have only 0, 1, X and Z.

 

[sun_ray]

If by binary you mean integral value and non-binary you mean real; it is legal, though not very useful.

By binary I mean binary numbers (011, 111, 101......) or numbers represented in binary system. By non binary I mean numbers not in binary system ( 10, 12, 1A. 5D.....) or numbers represent in a base system different than binary system. The numbers will be integer of course here as they are case items for casex and casez. Please now answer to my query.

 

[FvM]

See IEEE 1364:

An x represents the unknown value in hexadecimal, octal, and binary constants. A z represents the highimpedance value. See 4.1 for a discussion of the Verilog HDL value set. An x shall set 4 bits to unknown in the hexadecimal base, 3 bits in the octal base, and 1 bit in the binary base. Similarly, a z shall set 4 bits, 3 bits, and 1 bit, respectively, to the high-impedance value.

It's usage for casex and casez isn't explicitely discussed in the standard. You should check if your tools support it.

 

[sun_ray]

FvM

It is not answering my question. Can we put 3'd6, 4'h5 in case items for casex and casez?

 

[FvM]

You are slowly approaching a clear question. Of course you can.

 

[dave_59]

3'd6 and 4'h5 have binary representations; 3'b110 and 4'b0101 are equivalent as far as what the simulator sees. But casex and casez are of no use unless there is an X or Z in one of the case expressions.

 

[krishanu007]

it is advised not to write casez or casex for to-be-synthesized code as it may show non-parallel property & leading to a priority mux structure while synthesized..
which may not be what you are intended to.