Verilog conditional operator

Muthuraja.M · Nov 17, 2014

Hi friends,

I need to know about the conditional operator clearly. Even though i do some of the examples as mux using conditional operators. But i didn't understand wat actually doing in the below code..

Code Verilog - [expand]
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module rumania(gate, D, Q);             
 
parameter Bi = 16;
parameter prop_delay = 0;
 
input gate;
input [Bi-1:0] D;
output [Bi-1:0] Q;
 
assign   Q = gate ? ((D[Bi-1] & !(|D[Bi-2:0])) ? 
    {1'b0, {(Bi-1){1'b1}}} :
      (- D)) : D;                                
 
endmodule

Actually this code has the inverting of input as its output when the gate is logic'1' and give the input as it the output when the gate is logic'0'.

But i need the operation used in this code.

Please clarify this..

Thanks in advance...

sharath666 · Nov 17, 2014

1.First check the value of gate.
2.If gate=1, it then checks for D[Bi-1] & !(|D[Bi-2:0]).
3.If gate=0, then it assigns D to Q.(last D in statement).
4.If D[Bi-1] & !(|D[Bi-2:0] is true, then it assigns {1'b0, {(Bi-1){1'b1}}} to Q.
5.If D[Bi-1] & !(|D[Bi-2:0] is false then it assigns -D to Q.

I don't know what is -D..Or was it ~D?

Muthuraja.M · Nov 17, 2014

Sharath666

Thank u very much..

I got it..

Verilog conditional operator

Muthuraja.M

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sharath666

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Muthuraja.M

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Verilog conditional operator

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