Verilog Conditional assign statements

Hi..
Can we use multiple assign statements for a single condition?
for example
case(condition)
begin
a1=b1;
a2=b2;
a3=b3;
end
i tried this. there was no compilation error. Still the value was not getting assigned when running the simulation.
Is there any alternative to do this? Please help.

Hang on - my telepathy brain is out on loan today, so I have no way of understanding what you're on about.

Why not post the whole code and specifically say whats not being set and when so I dont need to ask for the brain back.

Yes you can, provided you actually follow the case statement syntax.

So something like:

Although given your choice of variables it just might be that you are trying to do something creatively impractical, I'm not sure.

Yeah. I did follow the syntax.
I m generating a set of 75 values in a module and i m trying to pass it to another module
where the conditional assignments are needed.
this is a piece of my code.

always @(m1,kk01,kk02,kk03,kk11,kk12,kk13,kk21,kk22,kk23,kk31,kk32,kk33,kk41,kk42,kk43,kk51,kk52,kk53,kk61,kk62,kk63,kk71,kk72,kk73,
kk81,kk82,kk83,kk91,kk92,kk93,kk101,kk102,kk103,kk111,kk112,kk113,kk121,kk122,kk123,kk131,kk132,kk133,kk141,kk142,kk143,kk151,kk152,kk153,kk161,
kk162,kk163,kk171,kk172,kk173,kk181,kk182,kk183,kk191,kk192,kk193,kk201,kk202,kk203,kk211,kk212,kk213,kk221,kk222,kk223,kk231,
kk232,kk233,kk241,kk242,kk243,kk251,kk252,kk253)

case(m1)
5'b00000:
begin
k01=kk01;
k02=kk02;
k03=kk03;
end


5'b00001:
begin
k01=kk01;
k02=kk02;
k03=kk03;
k11=kk11;
k12=kk12;
k13=kk13;
end

5'b00010:
begin
k01=kk01;
k02=kk02;
k03=kk03;
k11=kk11;
k12=kk12;
k13=kk13;
k21=kk21;
k22=kk22;
k23=kk23;

end
endcase

i have declared kk01,kk02 etc.. as wire[16:0] since i m passing it on from another module. k01,k02 etc.. as output reg[16:0].
when running the simulation i can see the program control to go into the loop. but still the values were not being assigned to the destination variable.
I m a beginner in verilog. Kindly help.
Thank you for your reply.