Verilog Compile Problem

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davyzhu

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verilog expecting a statement

Hello all,

There are three compile problem,

[1] address[15:0] = {addr[7:0],address_low[7:0]};
the "address" and "address_low" is reg and "addr" is input,

the errors are
near "[": expecting: IDENT,
near ",": expecting: '('
near "}": expecting: '('

[2]else if (!ale_n and psen_n and (address[15:8] == BASE_ADDR))

the errors are
near "and": syntax error
near ")": expecting: ',' ';'

[3]case (address[7:0])
STATUS_ADDR:

the errors are
near "STATUS_ADDR": expecting: ';'

BTW, what is the IDENT?

Regards,

Davy Zhu
 

verilog compile

Are you sure you compile for verilog, and not vhdl?

Syntax seem correct, hard to tell without the context source code.

You may have forgotten a 'begin' or some other statement before the errors, ex:

always@(posedge clk)
statement 1;
statement 2;
statement 3;

Then, you're in for strange errors...
 

expecting: ident

Hello all,

I found the answer myself,
[1] addr must be "wire"
[2] replace "and" with &&
[3] miss "endcase"
 

verilog expecting: ident

[3] if the statement is empty, you should add ";" after it. And use "endcase" to end case sentence.
 

** error: verilog compiler exiting

BTW, what is the IDENT in modelsim?

It always appares in compile errors.

Regards,

Davy Zhu
 

modelsim expecting ident

IDENT is short for IDENTifier, as in 'expecting identifier'.
 

verilog expecting <=, or =

reg type can't be assign to a wire type ,
use & or && to replace "and"
 

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