davidgrm
Full Member level 4
combinational loop
Hi
Why would this code cause a combinational loop on Delay?
always @(clk)
begin
if(!CPU_WR || !FPGA_WR)
begin
Delay <= 2'b10;
end
else
begin
Delay <= Delay - 1'b1;
end
end
Hi
Why would this code cause a combinational loop on Delay?
always @(clk)
begin
if(!CPU_WR || !FPGA_WR)
begin
Delay <= 2'b10;
end
else
begin
Delay <= Delay - 1'b1;
end
end