Verilog Combinational Loop - Help Required

[davidgrm]

combinational loop

Hi

Why would this code cause a combinational loop on Delay?

always @(clk)
begin
if(!CPU_WR || !FPGA_WR)
begin
Delay <= 2'b10;
end
else
begin
Delay <= Delay - 1'b1;
end
end

 

[tkbits]

combinational loop in verilog

It's not clocked on an edge. So a register is not created. Choose a positive or negative edge for the clock.

Without a clock edge, the following is a combinational loop:

Delay <= Delay - 1'b1;