Verilog Coding style questions

[pyrite]

Hi,
I have few questions on the verilog coding style.

Which is better in term of speed/area for synthesis?
Question 1:
a. I can create some small functions such as a function that will do add, a function that will do multiplication. So that every time when I need to do some multiplication (example), i can just call this function.
b. Or I can do the multiplication/addition simply in the code without using functions.

Question 2 (related to question 1):
a. Use function.
b. Use submodule.

Question 3:
a. always @(posedge clk)
a <= b + c;
b. assign d <= b + c;
always @(posedge clk)
a <= d;

Question 4:
a. if (b == 3'b111)
.........
b. assign a = &b;
if (a)
.........


Thanks in advance!

Jeff

 

[javad]

OK! First note that a good coding style may vary from one fpga family to another. So see the synthesizer tool document to find more.
But about your questions:
1. You can do that. But simply you can use * for multiplication. On devices such as Virtex-II and Spartan-III, this will synthesized to Embedded multipliers.
2. I advise to use submodules.
3. No difference!
4. No difference!

A practical way to find the replies of these questions is to write a simple code and examine them with synthesis. Then see the result circuit!

 

[z81203]

mine opinion is for logic, use submodule; for stimulus, use function.