verilog code of 8 dct architecture

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riti1

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i write the code for 8 dct...but i am getting certain warnings which i cant able to reolve.guide me for the same.

Code Verilog - [expand]
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module dct_8(clk,x0,x1,x2,x3,x4,x5,x6,x7,y0,y1,y2,y3,y4,y5,y6,y7
    );
input clk;
input [3:0] x0,x1,x2,x3,x4,x5,x6,x7;
output [11:0] y0,y1,y2,y3,y4,y5,y6,y7;
wire[10:0] t089,t075,t050,t018,t189,t175,t150,t118,t289,t275,t250,t218,t389,t375,t350,t318;
wire[4:0] f0,f1,f2,f3,z0,z1,z2,z3;
 
input_adder_8 m(clk,x0,x1,x2,x3,x4,x5,x6,x7,f0,f1,f2,f3,z0,z1,z2,z3);  //a0=f0,b0=z0
new w(clk,f0,f1,f2,f3,y0,y2,y4,y6);
shift_adder_8 p0(clk,z0,z1,z2,z3,t089,t189,t289,t389,t075,t175,t275,t375,t050,t150,t250,t350,t018,t118,t218,t318);
 
 output_adder_8a q(clk,t089,t318,t175,t250,y1);
 output_adder_8b r(clk,t289,t118,t075,t350,y3);
 output_adder_8c s(clk,t189,t218,t375,t050,y5);
 output_adder_8d t(clk,t389,t018,t275,t150,y7);
 
endmodule
 
 
 
module input_adder_8(clk,x0,x1,x2,x3,x4,x5,x6,x7,f0,f1,f2,f3,z0,z1,z2,z3);
input clk;
input [3:0] x0,x1,x2,x3,x4,x5,x6,x7;
output reg[4:0] f0,f1,f2,f3,z0,z1,z2,z3;
 
always@(posedge clk)
begin
 
 f0<=x0+x7;
 z0<=x0-x7;
 f1<=x1+x6;
 z1<=x1-x6;
 f2<=x2+x5;
 z2<=x2-x5;
 f3<=x3+x4;
 z3<=x3-x4;
 end
endmodule
 
 
module shift_adder_8(clk,z0,z1,z2,z3,t089,t189,t289,t389,t075,t175,t275,t375,t050,t150,t250,t350,t018,t118,t218,t318);
input clk;
input [4:0]z0,z1,z2,z3;
output reg[11:0]t089,t075,t050,t018,t189,t289,t389,t175,t275,t375,t118,t218,t318,t150,t250,t350;
reg [6:0] u0,u1,u2,u3,v0,v1,v2,v3;
 
always@(posedge clk)
begin
 
 u0 <= (z0<<3)+z0;
 u1 <= (z1<<3)+z1;
 u2 <= (z2<<3)+z2;
 u3 <= (z3<<3)+z3;
 v0 <= (z0<<4)+u0;
 v1 <= (z1<<4)+u1;
 v2 <= (z2<<4)+u2;
 v3 <= (z3<<4)+u3;
 t089 <= (z0<<6)+v0;
 t189 <= (z1<<6)+v1;
 t289 <= (z2<<6)+v2;
 t389 <= (z3<<6)+v3;
 t075 <= (v0<<1)+v0;
 t175 <= (v1<<1)+v1;
 t275 <= (v2<<1)+v2;
 t375 <= (v3<<1)+v3;
 t050 <= (v0<<1);
 t150 <= (v1<<1);
 t250 <= (v2<<1);
 t350 <= (v3<<1);
 t018 <= (u0<<1);
 t118 <= (u1<<1);
 t218 <= (u2<<1);
 t318 <= (u3<<1);
 end
endmodule
 
module output_adder_8a(clk,t089,t175,t250,t318,y1);
input clk;
input [11:0] t089,t175,t250,t318;
output reg[15:0] y1;
reg [12:0] c,d;
 
always@(posedge clk)
begin
 
 c<= t089+t318;
 d<= t175+t250;
//assign e= t89+t18;
//assign f= t75-t50;
//assign g= t18-t89;
//assign h= t75+t50;
//assign i= t18-t89;
//assign j= t75-t50;
 
 y1<= c+d;
//assign y3= e+f;
//assign y5= g+h;
//assign y7= i+j;
end
endmodule
 
module output_adder_8b(clk,t289,t075,t350,t118,y3);
input clk;
input [11:0] t289,t075,t350,t118;
output reg[15:0] y3;
reg [12:0] e,f;
always@(posedge clk)
begin
 e<= t289+t118;
 f<= t075-t350;
 y3<=f-e;
 end
endmodule
 
module output_adder_8c(clk,t189,t375,t050,t218,y5);
input clk;
input [11:0] t189,t375,t050,t218;
output reg[15:0] y5;
reg [12:0] g,h;
always@(negedge clk)
begin
 g<= t218-t189;
 h<= t375+t050;
 y5<=g+h;
 end
endmodule
 
module output_adder_8d(clk,t389,t275,t150,t018,y7);
input clk;
input [11:0] t389,t275,t150,t018;
output reg[15:0] y7;
reg [12:0] i,j;
always@(posedge clk)
begin
 i<= t018-t389;
 j<= t275-t150;
 y7<=i+j;
 end
endmodule



 
Last edited by a moderator:

These warnings can be ignored. These are reported because your design is an overkill. The unnecessary logic has been optimized away. So for every bit optimized away, it reports a warning message. Go through the warning message & relate it to your design. You will understand the meaning.
 

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