Verilog Code Is Not Producings The Expected Results

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luyunfei330

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I'm fresh about verilog,please help me find out where the mistake is.
Code: 
  reset=1;
  #10 @(posedge clk);
  enable=1;
  #30 @(posedge clk);
  enable=0;
  #100 $finish;
 
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in what context? is this mean to be testbench code? or synthesisable (because it very much isnt).
 

Hello,

Remove the ";" from "@(posedge clk)" on lines 2 and 4. Once you put them, you are basically doing nothing when posedge clock is detected.
 

pbernardi said:
Hello,

Remove the ";" from "@(posedge clk)" on lines 2 and 4. Once you put them, you are basically doing nothing when posedge clock is detected.
Click to expand...

No, that isn't a problem.

I'm not sure what the OP's problem is but the code posted works fine, as long as you generate a clock.
Code Verilog - [expand]
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module test2;
 
reg clk, reset, enable;
initial begin  
  clk = 0;
  forever clk = #100 ~clk;
end
 
initial begin
  reset=1;
  #10 @(posedge clk);
  enable=1;
  #30 @(posedge clk);
  enable=0;
  #100 $finish;
end
 
endmodule



Perhaps the OP should define what they are expecting the results should be.

Regards

- - - Updated - - -

Forgot to mention the #10 and #30 really don't do anything as long as the clock period is bigger than the time control statement. They actually should be removed as the @(posedge clk) is the only time control statement that is doing something useful.

If those #10 & #30 were moved to after the @(posedge clk) then the assignment of enable would be delayed accordingly.
 

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