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Verilog code for stepper motor

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meehd0

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Hi everyone. I have a 6 wire unipolar stepper motor connected to a L298 H-Bridge. Now I'm trying to control the speed and direction of the motor on a spartan-3e. I tried searching for source code to get me started but most of them are in VHDL and only controls the direction of the motor. I was hoping someone can provide me with some insight on how to start the code, preferability in Verilog.

Thanks
 

sample code

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sequencer is
	port(
		rst_n		: in	std_logic;
		enable	: in	std_logic;
		direct	: in	std_logic;
		clock		: in	std_logic;
		x			: out	std_logic;
		xbar		: out	std_logic;
		y			: out	std_logic;
		ybar		: out	std_logic
	);

end sequencer;

architecture mjb of sequencer is

signal x_int	: std_logic;
signal y_int	: std_logic;

begin

	process(rst_n,clock)
	begin
		if(rst_n = '0') then
			x_int <= '0';
			y_int <= '0';
     	elsif(clock'event and clock = '1') then
			if(enable = '1') then
	    		x_int <= direct xor y_int;
	    		y_int <= direct xnor x_int;
			else
	    		x_int <= x_int;
	    		y_int <= y_int;
			end if;
     	end if;
  	end process;

  	x <= x_int;
  	y <= y_int;
  	xbar <= not x_int;
  	ybar <= not y_int;

end mjb;
 

To achieve the intended phase sequence, the next states of x_int and y_int need to depend on the previous states of both phases respectively. The below code doesn't work this way:
Code:
x_int <= direct xor y_int;
y_int <= direct xnor x_int;
P.S.: Everything is working correct! My fault.

So the next point would be a step speed generator, that sets "enable" each Nth clock cycle.
 
Last edited:

So the next point would be a step speed generator, that sets "enable" each Nth clock cycle.

Thanks both of you guys for the help, the motor is running... but pretty slow. But I'm alittle confused by what you mean by "enable each Nth clock cycle". Can you elaborate?
 

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