verilog code for serial in parallel out shift register

Code Verilog - [expand]
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module trai1enc( din ,clk ,reset ,dout );
output [2:0] dout ;
wire [2:0] dout ;
input [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [2:0]s;
initial s=0;
assign din[0]=1;
assign din[1]=0;
assign din[2]=0;
assign din[3]=1;
genvar i;
for (i=0;i<=3;i=i+1)
begin
if (i==0)begin     //i=0
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[0];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else if (i==1)begin  //i=1
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[1];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else if (i==2)begin //i=2
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[2];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else begin
always @ (posedge (clk)) begin //i=3
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[3];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
end
endmodule

Code Verilog - [expand]
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parameter SWIDTH = 16;
reg [SWIDTH-1:0] shift_reg;
always @ (posedge clk) begin
  if (shift) begin
    shift_reg <= {shift_reg[SWIDTH-2:0], serial_in};
  end
end