Verilog code for pid controller

I am doing a project on ic design for speed control of a dc motor..so plz help me with a verilog code pid controller..where i can input the eroor value and get the ouput as my desired value...thankss in advance

Actually I wasn't going to answer this. But I realized if I won't, no one is going to tell the things I'm going to tell you . Hear me bro:

1- The PID controller design is a very serious business. There is a whole section of engineering, namely the control engineering, related to it. So I wish it were that easy like plug and control. So you need model of your DC motor, and lots of simulink simulations. Actually there might be some samples from fpga manufacturers, but I don't know.

2- Do not expect to find a magical open code for "Mystical Box for PID Control". Some companies do have generic designs, however they do not share it. If you are able to write one, do share with us

3- One last thing is if you are doing a project on it, it means that you are venturing around the limits of the human knowledge. So you should be expecting undiscovered lands, at least undiscovered for you, expect harsh working conditions, sleepless nights and grinding as used in gaming.

So I believe I didn't answer your question, but hopefully these will help in your engineering carreer. At least I would have wished someone told me these. As a result, do not expect help when asking questions like "how to design best circuit in the world", ask help for the problems in your path. And from your question I can understand that you haven't worked on PID controllers anyway.

Edit: Man this sounded like a motivational speech. Anyway that wasn't my intention. My intention was to tell you why your question won't get an answer.

really thankful for ur advice...i already have designed one pid and is getting simulated individually...but my project consists of modules a counter,pid and pwm...and when i am trying to link the three modules i am getting it compiled successfully but i am not getting the output of pid correctly...i tried it in many ways...i went to many conditions as u mentioned earlier like sleepless nights an al...but still i cant get it corrected thats y i want to refer to some other models of pid so that i can find out what is the actual problem with my design..

when i am trying to link the three modules i am getting it compiled successfully but i am not getting the output of pid correctly...

Click to expand...

So your next task is learning how to debug Verilog code. Did you already hear the terms simulator and testbench?

So you need model of your DC motor, and lots of simulink simulations.

Click to expand...

He asks about PID design, not PID tuning !

Malek Lamari said:

He asks about PID design, not PID tuning !

Click to expand...

Well, in order to design a PID controller (The things written beyond this point is completely my own experience which is very little. Feel free to correct me if I'm wrong.), I believe models should be included. The thing is a PID controller with random coefficients are not going to work. I mean it might but it would be very lousy and more importantly it wouldn't teach anything to the guy who is asking the question, which I believe is the most important thing. Sorry if my writing offended you, I was trying to point out that none of the "how to design satellites" or similiar threads are answered in this forum.

So I stand behind my comment, you "do" need simulations and models to actually "design" a PID controller, not just for tuning it.

For answers above, it looks you are learning Verilog, but you know PID or not? More specificaly, what is you problem: you undertand the PID algorithm, but does not know how to implement in Verilog, or you know Verilog and doesn´t know about PID, or you don´t know both?

If you know C, there are some generical PID examples available on internet (google is your friend). Once you *understand* the PID process (when you understand what C code does, the coding is much simplier!), then you could try to port a code to Verilog.

Please note, in any time I said that Verilog and C are equal, so it is not a C-Verilog translation task.