verilog code for LFSR

[rockgird]

lfsr verilog

hii,
i m writin a code for a 1-bit LFSR. but it isn't workin.

this is my code


module LFSR ( out ,clk );

input clk ;
wire clk ;

output out ;
wire out ;

reg Q1='b1;
wire Q2='b1, Q3='b1;
wire i='b0;


task dff;
output Q;
input D;
begin

assign Q = D;
end
endtask


always @(posedge clk)
begin
while(i<1)
begin

assign Q1=((Q2&(~Q3))|((~Q2)&Q3));
dff (Q2,Q1);
dff (Q3,Q2);
dff (Q1,Q3);
end;
end

endmodule


this is the error i m gettin

# Compile...
# Pass 1. Scanning modules hierarchy.
# Pass 2. Processing instantiations.
# Pass 3. Processing behavioral statements.
# Error: VCP2808 LFSR.v : (53, 14): Q OUTPUT/INOUT argument in dff task must be connected to a valid left-hand side of procedural assignment: Q2.
# Error: VCP2808 LFSR.v : (54, 14): Q OUTPUT/INOUT argument in dff task must be connected to a valid left-hand side of procedural assignment: Q3.
# Error: VCP2000 LFSR.v : (56, 5): Syntax error. Unexpected token: ;. Expected tokens: '#' , '(' , '{' , 'assign' , 'begin' ... .
# Compile failure 3 Errors 0 Warnings Analysis time : 1.
# done



block diagram is attached



ps:- I m usin Active HDL 6.3 for this person.


thanx in anticipation.

 

[ravurig]

lfsr verilog code

You can try with the following code.

always @(posedge CLK or negedge RST_X) begin
if(!RST_X) begin
Q1_REG <= 'd0;
Q2_REG <= 'd0;
Q3_REG <= 'd0;
end
else begin
Q1_REG <= n_Q1_REG;
Q2_REG <= n_Q2_REG;
Q3_REG <= n_Q3_REG;
end
end

assign n_Q1_REG = Q2_REG ^ Q3_REG;
assign n_Q2_REG = Q1_REG;
assign n_Q3_REG = Q2_REG;

 

[raju_edaboard]

verilog lfsr

This will shifts the contents from MSB to LSB.

module lfsr #(parameter LFSR_WIDTH = 8,
TAP0 = 0,
TAP1 = 2,
TAP2 = 3,
TAP3 = 4)
(input clk,
input rst_n,
input din,
input load,
input shift,
output reg [LFSR_WIDTH-1:0] Q
);


reg [LFSR_WIDTH-1:0] Q_next;

always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
Q <= {LFSR_WIDTH{1'b1}}; //Initialize LFSR to all ones
else
Q <= Q_next;
end


// XOR the taps
assign taps = Q[TAP0] ^ Q[TAP1] ^ Q[TAP2] ^ Q[TAP3];

//Calculate next state of the output
always @*
begin
Q_next = Q; // Default next state. (No shift)

if(load) //load din
Q_next = {din,Q[LFSR_WIDTH-1:1]};
else
if(shift) //shift the contents of Q with taps
Q_next = {taps,Q[LFSR_WIDTH-1:1]}; // Feedback is connected to FF[LFSR_WIDTH-1]
end

endmodule

 

[OutputLogic]

lfsr in verilog

You can use an online tool that will generate Verilog code for LFSR:
OutputLogic.com

Hope that helps[/url]