Verilog code for CRC (7-bits) calculation

[SystemEngineer]

Hello ,

I need to generate CRC (7-bits) for a 40-bit data input.

I know the following:
G(x) [Generator polynomial]
M(x) [40-bits Polynomial]

Can anyone please guide me to write the verilog code?

Thanx,
eagerly waiting...
Please Reply at: iamyourengineer2004 AT hotmail DOT com

 

[dainis]

crc7 calculation

/http://www.easics.be/webtools/crctool

 

[wadaye]

crc-7 calculator

The detail complementation by hardware is depending on whether the data is serially or parallel, and whether the default value in regs are 0 or 1, both of them can work, but you will get different hardware.

Another thing you should think is whether you wanna get the CRC result as soon as the data input finish or after some cycles, this will cause different hardware too.