Verilog code : division of 2 numbers (8bit)

popdog22 · Nov 2, 2013

The module I have to use is this one:

Code Verilog - [expand]
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module divider(
output reg[7:0] q,         
output reg[7:0] r,
input [7:0] a,b);
endmodule

where a=b*q+r

I'm not allowed to use repetitive subtracting or the / and % operators.

Any help?

FvM · Nov 2, 2013

You can either use bitweise shift and substract (serial divider) or fast parallel division algorithms (rather complex) https://en.wikipedia.org/wiki/Division_algorithm

popdog22 · Nov 2, 2013

Yes, but I don't know the algorithm for those moethods

Code Verilog - [expand]
1 2 3 4 5	module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a,b); endmodule

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