Verilog code Divide by 2.5

[pmoonlite]

I have a 25 MHz but need 10 MHz, will you please let me know how to write the verilog code for divide by 2.5. This is what I have done, but not sure if it will work. I have divide by 5 and multiple by 2.

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Code Verilog - [expand]
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always @(posedge CLK_OSC or posedge RST)
 if (RST)
 count<=0;
 else if (count == 3'd4)
 count<=0;
 else 
 count <=count+1;
 
 assign clkA = count[1];
 
 always@(negedge CLK_OSC )
 clkB <= clkA;
 
 assign clk5_Mhz = clkA | clkB;
 assign clk10_Mhz = clk5_Mhz <<1;

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[pbernardi]

There is an internal component on most FPGAs that does this. Use it: PLL or DCL.

Check your FPGA datasheet.

 

[ads-ee]

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Code Verilog - [expand]
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assign clk10_Mhz = clk5_Mhz <<1;

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How is taking a 1-bit signal and shifting it up one bit and assigning it to another 1-bit wide signal supposed to multiply the frequency of the signal by 2 (this pretty much says assign 0 to clk10_Mhz)? I think you've got frequency multiplication confused with number multiplication.

Use a PLL or DCM as pbernardi tried to suggest. If your FPGA doesn't have them, then you should consider using a better FPGA.

 

[pmoonlite]

This is my issue, I do not have a FPGA, I have a CPLD with limited resource. At this time, I can not change
the design. I appreciated if you have any other idea that you can share. Do you have any code that
allow me to go from 25Mhz to 10Mhz? thanks

 

[std_match]

Do you need a "clean" clock, or is it acceptable with a lot of jitter?
If jitter is acceptable, a possible solution might be to use the 25 MHz clock with a clock enable to only enable 2 of every 5 cycles.

The net effect would be identical to a clock like this:

___-___-_____-___-_____-___-_____-___-_____-_ (10 MHz clock with jitter, example)

_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ (25 MHz original clock)

 

[pmoonlite]

sorry I need a clean clock (

 

[andre_luis]

a possible solution might be to use the 25 MHz clock with a clock enable to only enable 2 of every 5 cycles

I presume the reduction from 25MHz to 10MHz should be due to timing constraints of the circuit, so that eliminating of some pulses could not suffice.

 

[pmoonlite]

My limitation is hat I can not change the hardware, all the changes need to happen in the verilog code, my only
input into CPLD is clock in= 25Mhz + Reset and clock out from CPLD. There are some timing issue this is
the reason I am trying to reduce the freq to 10Mhz.

 

[ads-ee]

There are some timing issue this is the reason I am trying to reduce the freq to 10Mhz.

Those are some pretty big timing issues!?

25 MHz = 40 ns period i.e. 40ns for Tco+Tpd+Tsu+Tskew
which becomes 100ns for the same setup constraint.

Seems to me a timing problem that requires 60ns more time is not a timing problem it's a design problem. If this isn't the case then this is just another case of a newbie Edaboard member not asking a clear question or even the right question with supporting information for others to make truly helpful suggestions.
e.g. not including information about the constraints of the problem being in a CPLD or even which CPLD, not including the can't change hardware, not including what the actual problem is with timing, not including why you need a reduction in clock frequency of 25 MHz down to 10 MHz.

Providing a snippet of code that is useless (generates a 0 Hz clock output) and asking if it will work isn't going to get you the answer you need (how to fix your problem).

What you currently want is to generate a 10MHz clock perhaps that is not what you need to do to actually fix the problem. Unfortunately we don't know what the problem really is.

 

[pbernardi]

It might be possible to delay your 25 MHz clock in 50% of the cycle, using verilog constraints. And then, you could make a XOR between your real clock and the delayed clock. This way, you can have a stable 50 MHz clock, making the division easier to 10 MHz.

But I fell really bad for suggesting this, I feel it is not the right way to face the problem.

And thank you for correction ads-ee, I am developing a hardware that have a signal named DCL, so this name is somehow glued on my mind.

 

[pmoonlite]

CPLD is XC9500XL family Device is XC9572XL. Package VQ44 Speed -10
Input to CPLD is Reset/25Mhz Clock
Output from CPLD Clock out
I have verilog Code in CPLD Clock out= 8.33 (25Mhz/3) no issue can read/write devices
I have verilog Code in CPLD Clock out = 12.25 MHz issue can not read/write devices
I would like Code to reduce the clock to 10Mhz to find out where is the break point.

Thanks

 

[ads-ee]

It might be possible to delay your 25 MHz clock in 50% of the cycle, using verilog constraints. And then, you could make a XOR between your real clock and the delayed clock. This way, you can have a stable 50 MHz clock, making the division easier to 10 MHz.

But I fell really bad for suggesting this, I feel it is not the right way to face the problem.

I considered mentioning something like this but it's not the way to get a clean clock, as pmoonlite desires (whatever "clean" means in clock specs). Over PVT the clock will vary in both duty cycle and jitter. Nominally your clock will be 50 MHz but with lots of jitter and a variable duty cycle.

Besides I was worried that pmoolite might become fixated on trying to fix their real problem with an even uglier duct tape and bailing wire fix.

 

[bking]

These are crude, but simple: **broken link removed**
They will also have latch generating issues, per the text.

 

[wade_hassler]

If you are just trying to find the 'break point', borrow a function generator for a few days.
Then go fix your design problem.