verilog code correction???

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sotomie

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can anyone please tell me if there is any logical error is this always block,its for fibonacci series ,i'm getting my results right but i was just curious if i've done something which isn't correct like using two 'if's?
Code Verilog - [expand]
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always@(posedge clock)
  begin
      if(n==0)
      current=1;
      else
      begin
      temp=current;
      current=current+previous;
      previous=temp;
      end
      if(current<previous)
      begin
            previous=0;
            n=0;
            current=1;
      end
    n=n+1;
   end   
endmodule
 
Last edited by a moderator:

No logical error, but bad style. Synchronous always blocks should use non-blocking statements for variable assignments.
 
Code: 
always@(posedge clock)
  begin
      if(n==0)
      current<=1;
      else
      begin
      temp=current;
      current=current+previous;
      previous=temp;
      end
      if(current<previous)
      begin
            previous<=0;
            n<=0;
            current<=1;
      end
    n<=n+1;
   end   
endmodule
better?
 

No, now you have mixed blocking and non-blocking statements for the same variables, which isn't allowed.
 

can you modify it ? I'm new to verilog.And if i am changing all the blocking assignments to non-blocking results are not right because of this part i think
Code: 
temp=current;
      current=current+previous;
      previous=temp;
.Thankyou
 

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