Verilog Code Checking Characters inputted simultaneously

Guys, I badly needed your help. I am a newbie to verilog and i have a problem with a certain exercise. Can anybody help me?

The problem goes like this:

A certain variable is already initialize with a value, in this case it would be "abc".
Then using 3 push buttons, the user will and must input the sequence correctly. In this case, the user must input "abc" simultaneously and correctly.
If the user will input "b" or "c" first, as in "bxx" or "cxx" respectively, it will result to display "E" as in error. Also if the user will input "acb" it would also be an error. Only "abc" is the correct format.


Please guys, help me..

I created a program in laravel to show you what I meant. If ever this could be of help, can you just convert this code to verilog? I badly needed you help guys.

Below is the code in laravel:
// array of sequence values
arr = ['a','b','c'];

// set current for initial value
current = 2; // array[current] evaluates to 'c'

for(; {
// get input and put to variable x
x = GETINPUT;

next = (current++ % array.length); // for first loop, next = (3%3) = 0 ; % is modulo
// compare x to the array
if(x == arr[next]) {
// TRUE
} else {
// ERROR
break;
}
}


Thanks a lot!..