[SOLVED] Verilog clock divider to go from 2.048MHz to 2Hz

[exgreyfox2]

Hello guys,

I am relatively new to FPGA/CPLD programming and I need to generate a 2Hz clock from a 2.048MHz clock. The 2Hz clock needs to be 50% duty cycle with pulse width of 250ms. Is it possible to implement a clock divider to do this? If so, can someone assist me in creating the Verilog routine? I've attached an image of what my output clock should look like.

Thank you kindly for any help.

 

[rhearty1]

Here's a good past post that goes through how to make a counter-based clock divider. This one is for 50 MHz to 1 kHz. You would just need to change two numbers (the count threshold and the midpoint, for 50% duty cycle) in order to use it for your two frequencies.

https://www.edaboard.com/threads/134194/

- Ryan

 

[exgreyfox2]

Will this code work for what I am trying to do? I found it here: **broken link removed**
I have a 2.048MHz clock and want to divide by 1,048,576 which is 2^20. After division I get 1.95Hz which is roughly the 2Hz I am looking for.

module clkdiv(clk_in,clk_out);
  input clk_in;
  output clk_out;
  reg [19:0] COUNT;

  initial COUNT=0;
  assign clk_out=COUNT[19];

  always @(posedge clk)
  begin
    COUNT = COUNT + 1;
  end
endmodule

I am trying to simulate the code with the following Xilinx ISE Test Bench but my output clock is a flat line. I am using the following test bench:

module Clock_Div_tb;

	// Inputs
	reg clk;

	// Outputs
	wire q;
	integer i; 

	// Instantiate the Unit Under Test (UUT)
	clkdiv uut (
		.clk_in(clk_in), 
		.clk_out(clk_out)
	);

	initial begin
		// Initialize Inputs
		clk_in = 0;
		
		// Wait 100 ns for global reset to finish
		#100;
		
		for(i=0; i<100; i=i+1)
		begin
			#244 clk_in = 1;
			#244 clk_in = 0;
		end
	end
endmodule

Can you guys please help? I am out of ideas.

 

[permute]

you want 2.048MHz. which is 2**14 * 5**3 (2**11 * 1000)

for the very slow clocks, this will work. Keep in mind that any signals passing between the "fast" clock and slow clock domains may need to meet timing. This becomes more difficult in FPGAs with this style of clocking. eg, if a signal can change on a 2.048MHz clock cycle and is expected to be registered by the 2Hz clock. Or if a register clocked by the 2Hz clock needs to be registered in the 2.048MHz domain. with a 2.048MHz input clock, this probably won't be an issue though.

For clocks of appreciable rate, it is more common to either use the dedicated clock division resources (divide by 8, or in some cases 128), or to use clock enables in the faster clock domain.

 

[exgreyfox2]

you want 2.048MHz. which is 2**14 * 5**3 (2**11 * 1000)

for the very slow clocks, this will work. Keep in mind that any signals passing between the "fast" clock and slow clock domains may need to meet timing. This becomes more difficult in FPGAs with this style of clocking. eg, if a signal can change on a 2.048MHz clock cycle and is expected to be registered by the 2Hz clock. Or if a register clocked by the 2Hz clock needs to be registered in the 2.048MHz domain. with a 2.048MHz input clock, this probably won't be an issue though.

For clocks of appreciable rate, it is more common to either use the dedicated clock division resources (divide by 8, or in some cases 128), or to use clock enables in the faster clock domain.

permute, the 2Hz signal is being used as a test input to some hydrophones and particle acceleration sensors. Basically I have available a 2.048MHz clock and need to get a 2Hz clock out of it to input to sensors as a test signal to see how they respond.

 

[Zampradeep]

..Just use a 10 bit or (0-1024) binary counter..carry output of 10th bit is 2 hz signal....

 

[exgreyfox2]

..Just use a 10 bit or (0-1024) binary counter..carry output of 10th bit is 2 hz signal....

This gives me a 2KHz clock with an input clock of 2.048MHz

 

[Zampradeep]

..O sorry use 20 binary bit counter..or 10 bit binary counter cascaded with 3(0-999) digit bcd counter..1024*1000=1.024m.....2.048m/1.024m=2 hz

 

[exgreyfox2]

That did the trick =D

Here is the working code for a 2Hz clock:

module Test_Mode_2Hz( //Test Mode 2Hz continuous clocking signal

en              ,                         //Enable clock divider 
SDCLK  	 ,		           //2.048MHz clock that is synchronous to the seismic sample clock (FIRSYNC)
CLK_2Hz      ,		           //Generated 2Hz Test Mode clock from 2.048MHz input clock
count				           //Clock divisor counter 
);

input clk_in, en;    
output clk_2Hz, count; 

reg [19:0] count = 0;
   
   always @(posedge clk)
		begin
			if (en == 1)
				count <= count + 1;
			end
			
	assign clk_2Hz = count[19]; 		
						
endmodule