verilog: calling other module to main module

romel_emperado · Aug 15, 2011

Hi all I have two modules and I want to call module a to my module b but I dont know how to do that.. any hint it's my first day of verilog.

I know it's possible. just like in C/C++ we include other files and call functions inside that file.. e.g. #include "test.h"

I want to use this method in verilog also.. I search in google but I cant find the answer..

---------- Post added at 12:27 ---------- Previous post was at 12:25 ----------

by the way here are the modules I want to combine..

segmentrial.v

PHP:

module segmentTrial(clk,clk2,min1,seg,seg_sel);


input clk;
output [7:0]seg;
output [3:0]seg_sel;
output clk2;
output min1;
reg [7:0]seg;
reg [3:0]seg_sel;
reg clk2;
reg min1;
integer i;

//parameter out = 8'b00000010;//6
parameter out = 8'b100_1111_0;
initial seg_sel = 4'b0001;


always@(posedge clk)
begin
	if(i==8000000) //divide by 80000 => 16MHz to 200Hz
	begin
		clk2=~clk2;
		i=1;
	end
	else 
	begin
		i=i+1'b1;
		
	end
	
end


/*always@(posedge clk2) 
	begin
		seg_sel={seg_sel[2:0],seg_sel[3]};
		
		if(seg_sel==4'b1000)	 seg = out;
		else if(seg_sel==4'b0100)seg = out;
		else if(seg_sel==4'b0010)seg = out;
		else if(seg_sel==4'b0001)seg = out;
		
	end
	
*/	
	

	
	

endmodule

decoder.v

PHP:

//this module allows numbes to be displayed in the 7 segment display.
//parameters declared like zero, one... are the numbers displayed in the 7segment.
module decoder(in,out);
parameter zero =8'b000_0001_1; //  3
parameter one  =8'b100_1111_1; //159
parameter two  =8'b001_0010_1; // 37
parameter three=8'b000_0110_1; // 13
parameter four =8'b100_1100_1; //153
parameter five =8'b010_0100_1; // 73
parameter six  =8'b010_0000_1; // 65
parameter seven=8'b000_1111_1; // 31
parameter eight=8'b000_0000_1; //  1
parameter nine =8'b000_0100_1; //  9
parameter blank=8'b111_1111_1; //255
input [3:0]in;
output [7:0]out;
reg [7:0]out;
always@(in)begin
	case(in)
	0:out=zero;
	1:out=one;
	2:out=two;
	3:out=three;
	4:out=four;
	5:out=five;
	6:out=six;
	7:out=seven;
	8:out=eight;
	9:out=nine;
	default:out=blank;
	endcase
end
endmodule

ckshivaram · Aug 15, 2011

if it is your first class then the example might be a bit complex for you...
you can understand it easily with few simpler examples at the beginning

Task And Function
Programmable Logic/Verilog Module Structure - Wikibooks, open books for an open world

---------- Post added at 17:39 ---------- Previous post was at 16:07 ----------

also a small discussion thread
Calling modules from Always block in VERILOG.

FvM · Aug 15, 2011

The usual way to assemble your Verilog design is instantiating modules, not calling functions (or modules). The difference matters, because the method is very different from calling C functions. It's more like soldering ICs to a board and connecting wires. If you want a second instance, you have to place a second IC.

Also functions, that are available for limited purposes, generate parallel hardware. Looking at hardware description languages from a software point of view is a popular way to completely misunderstand them. It's not impossible to learn things by trial and error, but much better to have a profound text book or tutorial. From the links given by ckshivaram, only the Wikibook is closely related to your question, I think.

A good reference for hardware related Verilog is the Synopsys reference manual

ckshivaram · Aug 15, 2011

yes FVM, i gave other link where your valuable suggestion is given in other forum... I came across that some time back, so i posted the other link tooo ..

romel_emperado · Aug 15, 2011

Thanks all of you guys.. Now I am practicing a basic approach to my hardware..

I got it working with simple counter from 1 to 9.. yeeeeeh! Im happy.. this is my first program in verilog and first time with FPGA.

PHP:

module segmentTrial(clk,clk2,min1,seg,seg_sel);


input clk;
output [7:0]seg;
output [3:0]seg_sel;
output clk2;
output min1;
reg [7:0]seg;
reg [3:0]seg_sel;
reg clk2;
reg min1;
integer i,hr;

//wire in,outd;


parameter one  = 8'b100_1111_1; //159
parameter zero = 8'b000_0001_1; //  3
parameter two  =8'b001_0010_1; // 37
parameter three=8'b000_0110_1; // 13
parameter four =8'b100_1100_1; //153
parameter five =8'b010_0100_1; // 73
parameter six  =8'b010_0000_1; // 65
parameter seven=8'b000_1111_1; // 31
parameter eight=8'b000_0000_1; //  1
parameter nine =8'b000_0100_1; //  9
parameter blank=8'b111_1111_1; //255 */


initial seg_sel = 4'b0001;
initial seg = blank;
//initial hr = 12;
//initial min = 1;


always@(posedge clk)
begin
	if(i==16000000) //divide by 80000 => 16MHz to 200Hz
	begin
		clk2=~clk2;
		i=1;
	end
	else 
	begin
		i=i+1'b1;
		
	end
	
end


always@(posedge clk2)
begin
	hr = hr+1'b1;
	if(hr == 60 || hr > 9 )
	begin
	seg = zero;
	hr = 0;
	end
	if(hr == 1) seg = one;
	if(hr == 2) seg = two;
	if(hr == 3) seg = three;
	if(hr == 4) seg = four;
	if(hr == 5) seg = five;
	if(hr == 6) seg = six;
	if(hr == 7) seg = seven;
	if(hr == 8) seg = eight;
	if(hr == 9) seg = nine;


end
 

endmodule

**broken link removed**

bigdogguru · Aug 15, 2011

FvM said:
Also functions, that are available for limited purposes, generate parallel hardware. Looking at hardware description languages from a software point of view is a popular way to completely misunderstand them. It's not impossible to learn things by trial and error, but much better to have a profound text book or tutorial.

I agree with FvM, this is one subject that calls out for a good textbook.

One of biggest hurdles newcomers encounter with any Hardware Description Language (HDL) like Verilog is the difference between a design which can be simulated and one the can be implemented.

An individual can easily produce a design which when simulated in ModelSim performs exactly as expected, however any attempt to implement the design in a real world FPGA offers anything but expected results.

It is learning the limitations of these real world devices, FPGAs, CLPDs, etc, that is key to a successful design and implementation with any HDL including Verilog.

I have numerous texts covering Verilog, however a few that are suitable as an introduction to the subject:

Verilog HDL (2nd Edition) - While lacking in the area of implementation, this text covers Verilog syntax quite well.

Verilog HDL Synthesis, A Practical Primer - Covers both syntax and implementation issues, supported by examples.

FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version - One of the best introductory/intermediate texts available, plenty of real world examples, however it is centered around Xilinx devices and development platform.

Verilog for Digital Design - A good solid introduction to Verilog

Hope the info helps in your new endeavors.

BigDog

romel_emperado · Aug 15, 2011

Thanks bigdogguro.. I will get that text books

we'll be back here.. Im still playing with FPGA..

bigdogguru · Aug 17, 2011

Here are a few online Verilog HDL tutorials, they are some the best of the bunch:

FPGA4FUN.COM - Lots of real world projects with excellent tutorials

Online Verilog Tutorial - ASIC World

**broken link removed**

These should help answer some of your questions that you've posted in this discussion thread.

BigDog

romel_emperado · Aug 17, 2011

Hi bigdogguro,

thanks for your recomended books.. I will surely get that all..

byt the way Im done with my digital clock but it is not the write way of doing this but Im happy for now I've done it..

I will improve this as soon as my knowledge in verilog also improves .. thanks so much
I will post my POOR code..

PHP:

module segmentTrial(clk,tick,seg,seg_sel);


input clk;
output [7:0]seg;
output [3:0]seg_sel;
output tick;
reg tick;
reg [7:0]seg;
reg [3:0]seg_sel;
integer i,r,minute1,second,minute2,hour1,hour2;


parameter one  = 8'b100_1111_1; //159
parameter zero = 8'b000_0001_1; //  3
parameter two  =8'b001_0010_1; // 37
parameter three=8'b000_0110_1; // 13
parameter four =8'b100_1100_1; //153
parameter five =8'b010_0100_1; // 73
parameter six  =8'b010_0000_1; // 65
parameter seven=8'b000_1111_1; // 31
parameter eight=8'b000_0000_1; //  1
parameter nine =8'b000_0100_1; //  9
parameter blank=8'b111_1111_1; //255 */


initial seg_sel = 4'b0001; //intialize seleector digit 1
initial seg = blank;  //initialize segment in to blank display

initial minute2 = 5;
initial minute1 = 9; 
initial hour2 = 1; 
initial hour1 = 2; 


/*---------- timer ---------------------*/
always@(posedge clk)
begin
	if(i==16000000) //1Hz
	begin
		i=1;
		second = second+1'b1;
		if(second == 60)
		begin
			second = 0;
			minute1 = minute1+1'b1;
			if(minute1 == 10)
			begin
				minute1 = 0;
				minute2 = minute2+1'b1;
				if(minute2 == 6)
				begin
					minute2 = 0;
					hour1 = hour1+1'b1;
					if(hour1 == 3 && hour2 == 1)
					begin
						hour1 = 1;
						hour2 = 0;
					end
					if(hour1 == 10) 
					begin
						hour1 = 0;
						hour2 = hour2+1'b1;
							
					end
				end
			end
		end
	end
	else 
	begin
	i=i+1'b1;  //increament i
	end
end




always@(posedge clk)
begin
	if(r==800)
	begin
		tick=~tick;
		r=1;
	end
	else 
	begin
		r=r+1'b1;
	end
	
end



always@(posedge tick) 
	begin
		seg_sel={seg_sel[2:0],seg_sel[3]};
		if(seg_sel==4'b1000)
		begin 
			
				case(hour2)	0:seg=zero;	1:seg=one;	2:seg=two;	3:seg=three;	4:seg=four;
				5:seg=five;	6:seg=six;	7:seg=seven;	8:seg=eight;	9:seg=nine;
				endcase

		end 
		else if(seg_sel==4'b0100)
		begin
		
				case(hour1)	0:seg=zero;	1:seg=one;	2:seg=two;	3:seg=three;	4:seg=four;
				5:seg=five;	6:seg=six;	7:seg=seven;	8:seg=eight;	9:seg=nine;
				endcase
		end
		else if(seg_sel==4'b0010)
		begin
				case(minute2)	0:seg=zero;	1:seg=one;	2:seg=two;	3:seg=three;	4:seg=four;
				5:seg=five;	6:seg=six;	7:seg=seven;	8:seg=eight;	9:seg=nine;
				endcase
		end
		else if(seg_sel==4'b0001)
		begin
				case(minute1)	0:seg=zero;	1:seg=one;	2:seg=two;	3:seg=three;	4:seg=four;
				5:seg=five;	6:seg=six;	7:seg=seven;	8:seg=eight;	9:seg=nine;
				endcase
		end
	end



endmodule

---------- Post added at 13:56 ---------- Previous post was at 13:46 ----------

**broken link removed**

bigdogguru · Aug 19, 2011

Hi Romel,

Here's an excellent resource for your MAX II Starter Kit. Complete with plenty of example Verilog Modules to implement various cores. Now you have some working modules by which to practice.

MAX II and MAX CPLD Design Examples

BigDog

romel_emperado · Aug 19, 2011

bigdogguru said:
Hi Romel,

Here's an excellent resource for your MAX II Starter Kit. Complete with plenty of example Verilog Modules to implement various cores. Now you have some working modules by which to practice.

MAX II and MAX CPLD Design Examples

BigDog

thanks so much bigdogguro... I sample projects are very useful based on it's description... I will do study this samples..

FvM · Aug 19, 2011

by the way Im done with my digital clock but it is not the write way of doing this but Im happy for now I've done it..

Not bad as a first attempt. I appreciate the clear synchronous design.

I would like to point to one aspect of Verilog programming. You are using "=" blocking assignments throughout the sequential "always@(posedge clk)"
blocks, like below:

Code:

second = second+1'b1; 
if(second == 60) 
  begin 
     second = 0;

This is similar to the way you would handle counting in a C program, but it's not the way, the FPGA works. So the Verilog compiler has to translate your code to something different like:

Code:

if(second == 59) 
  second <= 0;
else
  second <= second+1'b1;

Most textbooks suggest to use non-blocking "<=" assignments in sequential code. If you are proceeding to more complex designs, you'll see why.

romel_emperado · Aug 19, 2011

FvM said:
Not bad as a first attempt. I appreciate the clear synchronous design.

I would like to point to one aspect of Verilog programming. You are using "=" blocking assignments throughout the sequential "always@(posedge clk)"
blocks, like below:

Code:

second = second+1'b1; if(second == 60) begin second = 0;

This is similar to the way you would handle counting in a C program, but it's not the way, the FPGA works. So the Verilog compiler has to translate your code to something different like:

Code:

if(second == 59) second <= 0; else second <= second+1'b1;

Most textbooks suggest to use non-blocking "<=" assignments in sequential code. If you are proceeding to more complex designs, you'll see why.

Thanks so much FVM.. In my next adventure with FPGA I will follow your suggetion and I would learn new programming technique in verilog..

verilog: calling other module to main module

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