module top (control, A, B, C, RD, WR, CS_B, CS_C);
input [1:0] control;
inout [7:0] A, B, C;
input RD, WR;
output CS_B, CS_C;
assign B = (control == 2'b11 && WR) ? A : 8'bz;
assign A = (control == 2'b11 && RD) ? B : 8'bz;
assign C = (control == 2'b10 && WR) ? B : 8'bz;
assign B = (control == 2'b10 && RD) ? C : 8'bz;
assign C = (control == 2'b01 && WR) ? A : 8'bz;
assign A = (control == 2'b01 && RD) ? C : 8'bz;
assign CS_B = ~(control == 2'b11 && (RD || WR));
assign CS_C = ~((control == 2'b10 || control == 2'b01) && (RD || WR));
endmodule