[SOLVED] verilog :blocking and non blocking statments statments realization in hardware

Hi,

My question is,

A=B;
C=A; // blocking statments


A<=B;
C<=A; // non-blocking statements

how these 2 statements are realized in hardware?
whats their difference in hardware ?

thanks
smb

Combinational vs. sequential.

The 1st one is done with combinational cells, and the 2nd one works as shift registers therefore made with sequential cells.

Non-blocking means it does not block the execution of the next statement for the calculation of the destination. This means full parallel execution:


This will calculate the new A and B with the starting value for A and B from 'just' before the clock edge.
For example with A and B starting from 0:

A B
0 0 (startvalues)
1 2 (after first clock edge)
3 3
4 5
6 6
...

With blocking, however, the new value for the left hand side of the equation is assigned directly, and used on the next lines:


A B
0 0 (startvalues)
1 3 (after first clock edge)
4 6
7 9
10 12
...

To make it simple : use only non-blocking in clocked always blocks (this will generate flip-flops), use blocking in non-clocked always blocks (this will generate combinatorial logic).

Stefaan

It depends on the enviroment they are placed in. Assignments under an edge sensitive condition will create synchronous logic (flip-flops), other assignments will create combinational circuits and latches. This basic fact isn't changed by using blocking or non-blocking assignments. They onyl change the order and mutual dependency of statement evaluation.

Thanks for the response.
But still I am not clear.

I was being informed that

A=B;
C=A;

these 2 blocking statements are realized as only 1 flip flop,

and
A<=B;
C<=A;
these 2 non blocking statements are realized as 2 flip flops (as shift register),

How the 2 blocking stmts are realized with only 1 f/f?
Confusing.............

Request to clear my confusion
SMB

@shhelamb, im assuming the blocking/non-blocking stmts occur inside an always block
hence,for blocking statements, during any clock edge C gets assigned the value of A, where A is assigned the value B. Hence this becomes a flop where B is connected to D input of flop and C is connected to Q pin of the flop
(B --> A --> C ) is optimised by (B --> C)

in case of non-blocking assignment, during a clock edge A is assigned the value of B and C is assigned the previous value of A. Hence this is converted to a shift register with two flops.

hope this helps

chipmonkey,
If it is just 1 flip-flop (blocking stmt), it could be written as this C=B;
what is the importance of writting it in 2 stmts? i.e
A=B;
C=A;

sheelamb,

Like I already said, to stay out of trouble, use only non-blocking assigned in edge sensitive always blocks, and thus use only C<=B if you want one flipflop. I see no advantage in your 2 statement description with the blocking assignments.

It is a general adopted coding rule to do like this. Yes, you can describe the same logic in different ways, but there are some preferred scenarios. If you write code like the most of the people do, it is easier to understand each other code. Also the number of bugs will reduce.

You can find a lot information if you google for verilog coding rules...

Stefaan

sheelamb said:

chipmonkey,
If it is just 1 flip-flop (blocking stmt), it could be written as this C=B;
what is the importance of writting it in 2 stmts? i.e
A=B;
C=A;

Click to expand...

It's not about importance, but just a different way to write the same function.
In a programming language, or even human languages, there are many different ways to describe the same thing and the same applies to your verilog code.
Your question is like asking why verilog can write in different ways like below.

The code for "x" does not infer a register -- within the always block a new value is assigned to "x" before the old one is needed.

This code does infer a register for x. Notice that there is a line that uses the previous value of x.


IMPORTANT -- in both cases, the reg "x" cannot be used in other parts of the code safely. This is because process evaluation order isn't defined. A simulator might update "x" in always block 1 before it is used in always block 2. Or it might not. With nonblocking assigns, the simulator will determine the next values for all always blocks using the current inputs. It will then update all affects reg's at the same time. This makes the evaluation order of the always blocks unimportant.