Verilog Binary Counter

[forceface]

I'm currently working on a verilog module that has a binary counter and am I'm not quite sure what this binary counter is doing. The binary counter has 3 inputs (clock enable, synchronous reset and an internal clock) and one 32 bit
output. I'm having the output go to a led display where it shows the output of the counter in hexadecimal. In my mind this is how I see it working, each time clock enable goes high the binary counter starts counting till it gets to certain
value then resets and starts counting again. Then it displays how many times it gets to this value. Can someone confirm that I'm right and if set me straight. Thanks.

 

[permute]

no idea. look at the HDL.

I would have assumed:
if reset occurs and a rising edge of clock: count is set to 0
if clock enable and a rising edge of clock: count increments
if rising edge of clock without clock enable: count does not change.

the HDL should make the logic clear.

 

[shanmugaveld]

Clock enable is used to enable the internal clock.
if clock enable is not there then clock will not be generated and there wont be any operation.


Ususlaly for the simple binary counter they will use counter enable and it will work as "permute" explains above.
The counter will revert back to zero once it reaches the max value 2^32 - 1.