Verilog-ams vs Verilog-A

[ankitgarg0312]

please tell me difference in verilog-ams and verilog-a

i have read that verilog ams is super set of verilog-a , but can some body give me some examples of what features are in ams and not in verilog-a

 

[wpchan05]

please tell me difference in verilog-ams and verilog-a

i have read that verilog ams is super set of verilog-a , but can some body give me some examples of what features are in ams and not in verilog-a

I guess verilog ams is a mixed signal language where you can have analog and digital components. VerilogA is analog only.

 

[IADanilov]

Verilog-AMS = Verilog-A + Verilog-D (IEEE 1364 -1995)

 

[ankitgarg0312]

Verilog-AMS = Verilog-A + Verilog-D (IEEE 1364 -1995)

if v-ams also contains verilog-D.
can i synthesize it into gate level netlist??