Verilog-AMS simulation (Cadence Virtuoso)

[dirac16]

I tried to simulate the following Verilog code by AMS simulator:

module test(i1,i2,clk,sel,flag);

input i1, i2;
input clk;
output reg [1:0] sel;
output reg flag;

always @(negedge clk) begin
sel[1] <= i1;
sel[0] <= i2;
flag <= 1;

end

endmodule

Here's the output for the input test signals shown ( i1 : IN1, i2 : IN2, clk : CLK, flg : FLG and sel : SELO)

​

The output registers SELO<1:0> and FLG just before the falling edge of CLK are 0 and 1, respectively. That is not what I expect because before a falling transition occurs on CLK, the statements inside the always block are not executed, so neither FLG nor SELO<1:0> should have certain values before CLK's falling transition (Rather they must be evaluated to x). What's wrong? It's like the always block is executed at time 0. I changed negedge to posedge and ran the same simulation with CLK changed to a rising edge type. This time the outputs were evaluated to x before CLK's rising transition. So not sure why the code does not work for negedge.

 

[ThisIsNotSam]

show us the testbench.

 

[dirac16]

show us the testbench.

There is no testbench code for the simulation. I just created input test signals using vpulse from analogLib library. Then I connected the test signals to the symbol I created for the module. Here's the schematic:

 

[ThisIsNotSam]

ok. the problem is that you are trying to see x in an electrical simulator, not a logic simulator. there is no x, everything must settle to some DC state before the transient part of the simulation begins.

 

[dirac16]

ok. the problem is that you are trying to see x in an electrical simulator, not a logic simulator. there is no x, everything must settle to some DC state before the transient part of the simulation begins.

No, I'm running the simulation using ADE XL AMS simulator. I have made a config view of my schematic and did all the other setups correctly. It's not the first time I have used AMS simulator from Cadence. I just don't know what's the problem with this particular code.

 

[Shiyongjuan]

I tried to simulate the following Verilog code by AMS simulator:

module test(i1,i2,clk,sel,flag);

input i1, i2;
input clk;
output reg [1:0] sel;
output reg flag;

always @(negedge clk) begin
sel[1] <= i1;
sel[0] <= i2;
flag <= 1;

end

endmodule

Here's the output for the input test signals shown ( i1 : IN1, i2 : IN2, clk : CLK, flg : FLG and sel : SELO)

View attachment 173941
​

The output registers SELO<1:0> and FLG just before the falling edge of CLK are 0 and 1, respectively. That is not what I expect because before a falling transition occurs on CLK, the statements inside the always block are not executed, so neither FLG nor SELO<1:0> should have certain values before CLK's falling transition (Rather they must be evaluated to x). What's wrong? It's like the always block is executed at time 0. I changed negedge to posedge and ran the same simulation with CLK changed to a rising edge type. This time the outputs were evaluated to x before CLK's rising transition. So not sure why the code does not work for negedge.

No, I'm running the simulation using ADE XL AMS simulator. I have made a config view of my schematic and did all the other setups correctly. It's not the first time I have used AMS simulator from Cadence. I just don't know what's the problem with this particular code.

Hi! i have meet the same problem, i want to do a frequency division,

the following code dose not work:

---

Code Verilog - [expand]
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module test (input a, input b, output reg c );
always @(posedge a or negedge b) begin
if( !b) c <= 0 ;
else c <= ~c;
end
endmodule

---

however, this code works:

---

Code Verilog - [expand]
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module test (input a, input b, output reg c );
always @(a or negedge b) begin
if( !b) c <= o ;
else if(a == 0) c <= ~c;
else c <= c ;
end
endmodule

---

Sadly, the large part of my code is written as the first one, which can be verilfied in VCS, so what's the problem with ams simulator?

 

[ThisIsNotSam]

you folks need to revise the way sensitivity lists work and stop blame the "code".

 

[Shiyongjuan]

you folks need to revise the way sensitivity lists work and stop blame the "code".

i am the first time to use this simulator, can you tell me how to revise the way sensitivity lists work ? in the connect rules?

 

[rubink]

I was trying to work out a similar situation for a verilog model of a flip-flip simulation in Cadence AMS. The FF outputs were not starting as 'x' until a clock edge or reset as I expected. With a gate level model of the FF using nands the outputs would start as 'x'. Eventually I suspected there were events at time 0 even though nothing was changing then, so I added some test code:

in verilog code:

---

Code Verilog - [expand]
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initial begin
  $display("initial CK at time %0t, CK value %b",$time,CK);
  $display("initial CLR_n at time %0t, CLR_n value %b",$time,CLR_n);
end
 
always@(posedge CK) $display("posedge CK at time %0t, CK value %b",$time,CK);
always@(negedge CK) $display("negedge CK at time %0t, CK value %b",$time, CK);
always@(negedge CLR_n) $display("negedge CLR_n at time %0t, CLR_n value %b",$time,CLR_n);
always@(posedge CLR_n) $display("posedge CLR_n at time %0t, CLR_n value %b",$time, CLR_n);

---

===============

Results in log file

With both inputs starting low:

initial CK at time 0, CK value x
initial CLR_n at time 0, CLR_n value x
negedge CLR_n at time 0, CLR_n value 0
negedge CK at time 0, CK value 0

With both inputs starting high:

initial CK at time 0, CK value x
initial CLR_n at time 0, CLR_n value x
negedge CLR_n at time 0, CLR_n value 0
negedge CK at time 0, CK value 0
posedge CLR_n at time 0, CLR_n value 1
posedge CK at time 0, CK value 1

===============

So it seems like inputs start as x, then become 0, then change to 1 if the input is really high, all at time 0, but no transitions are visible in the waveforms.