[Verilog] Addressing signals from generate loops

Status
Not open for further replies.
K

knusprig

Newbie level 4
Joined
Sep 27, 2012
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,346
Hi,

I'm currently searching for a convenient way to solve the following problem in Verilog:

I created some module which includes the following code:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14

// somwhere in my module
parameter N=4;
genvar i;
wire reset_n;
 
generate
  for(i=0; i<N; i=i+1) begin: generatedModules
    anotherModule anotherModuleInstance
      (
        .reset_n_i (reset_n),
        ...
      );
  end
endgenerate


Now I want to build a testbench which sequentially tests these generated modules (they cannot work parallel for some reason). The testing requires that I force or read some signals within the "anotherModuleInstance"s. That wouldn't be a problem when I had a fixed number N. But I want to keep it variable so that I can easily change N to 3, 5, 127 or whatever.

Therefore I tried to use this for loop:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13

// in the testbench
parameter N=4;
integer k;
 
inital begin
  ...
  for(k=0; k<N; k=k+1) begin
    force generatedModules[k].anotherModuleInstance.reset_n_i = 1'b0;
    // test this and that
    // wait for tests of the instance to finish
    release ...;
  end
end


But if I try to simulate this code, it always comes up with this error: "Illegal operand for constant expression", pointing at the k in "force generatedModules[k].anotherModuleInstance.reset_n_i = 1'b0;".

When I replace the k with a fixed number, it works out fine. But I don't want to write down all ks explicitely. Is there another way?

Also I could use the generate statement in the testbench but my fear is that it will make things even more complicated as I would have to care much more about the temporal behaviour of the test to ensure that the modules still work sequentially. Is there another, simpler way?
 

First, try not to use force. Use variable at the top level that connect to ports and procedurally assign those variables.

There is no need to use a generate statement in your testbench because there is only one reset_n wire, assuming reset_n_i is a wire also.
 
Thanks for your feedback!

The generate statement is definitely needed in my testbench since I have to create a variable number of those modules. The modules aren't really feed by the exact same wire as my example code wrongly suggests (in fact they are barely connected), sorry for that.

However, I probably follow your recommendation and use those variables instead of the force statement. Unfortunately this means that I have break up the system on specific points. That was the reason why I was tempted to use "the force" in the first place.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…