edinburghtech
Junior Member level 2
Hello
I am trying to use Verilog-A to model a diode. This model will be attached to a spice netlist and simulated in spectre. I want to know if its possible to code the model in such a way that it behaves different to different simulations. (DC, AC, TRAN etc ). Please advise
Thanks
EdinTech
I am trying to use Verilog-A to model a diode. This model will be attached to a spice netlist and simulated in spectre. I want to know if its possible to code the model in such a way that it behaves different to different simulations. (DC, AC, TRAN etc ). Please advise
Thanks
EdinTech