Verilog-A mixed signal cadence adc

[lyko]

Verilog-A model for ADC

Dear All
It is posible to get a model of ADC using Verilog(including delay from clk to outputs and an input voltage to 10 or more bits binary numbers, even filter) Why is Verilog-A usually used in modelling ADC?
I am a beginner in Verilog-A. :-[
Thanks for your attention.
Lyko

 

[erikl]

Re: Verilog-A model for ADC

It is posible to get a model of ADC using Verilog(including delay from clk to outputs and an input voltage to 10 or more bits binary numbers, even filter)

The Cadence ahdlLib contains several examples (veriloga models) with 8bit ADCs and DACs, including ideal ones and setUps for DNL and INL measurements. Extensions for higher resolution should be easy. Delays and/or filters can/must be attached externally (there are veriloga models available, too).

Why is Verilog-A usually used in modelling ADC?

Because then you can simulate a system before the physical ADC is available.

 

[lyko]

Re: Verilog-A model for ADC

Thanks! I'll do some practices