verilog A difference between <= and <+

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Aforak

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hi dudes,

plz answer this
whats the difference between <= and <+ in verilog A

thank you
 

Hi Aforak,

From my understanding we must use the <+ when we are dealing with analog signals like V(out), I(in1, in2) etc. For driving these signals we need to use <+.

But if the signal is not an analog then we can use the <=.
 
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