Verilog A code for symmetrical charge pump

[vug]

I'm confused in writing the verilog A (analog Verilog) code for the above circuit in discrete domain ie, implemented in cadence virtuoso. This is a symmetrical charge pump using switched capacitor circuit. Can anyone help me with the code?

 

[nolanwrs]

uno online​

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I'm confused in writing the verilog A (analog Verilog) code for the above circuit in discrete domain ie, implemented in cadence virtuoso. This is a symmetrical charge pump using switched capacitor circuit. Can anyone help me with the code?

During the clock high phase, connect the positive input to the capacitor's positive terminal and the negative input to the negative terminal. This charges the capacitor to the voltage difference (inp - inn).

During the clock low phase, connect the positive terminal of the capacitor to the output and the negative terminal to ground. This transfers the stored charge to the output, creating a voltage on Vout proportional to the input voltage difference.

 

[vug]

This is the code i have written in z domain for the same circuit.
But the output is still zero.

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Code Verilog - [expand]
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`include "constants.vams"
`include "disciplines.vams"
 
module singlecpdis (vinp, vinm, voutp, voutm);
  inout vinp, vinm, voutp, voutm;
  electrical vinp, vinm, voutp, voutm, in, in1, in2, out, out1, out2;
//parameter real n=1;
// parameter real fsamp = 10e6; // Sampling frequency
//parameter real CL = 100e-12 from (0:inf); // Capacitance C
//parameter real CT = 100e-12 from (0:inf);
  parameter real G = 0.002;
  parameter real T = 0.1e-6;     // Sampling period
 
analog begin
 
V(in) <+ V(vinp)-V(vinm);
V(in1) <+ zi_nd(V(in),{1},{1},T);
V(in2) <+ zi_nd(V(in),{0,1},{1},T);
 
V(out) <+ V(voutp) - V(voutm);
V(out1) <+ zi_nd(V(out),{1},{1},T);
V(out2) <+ zi_nd(V(out),{0,1},{1},T);
 
I(in) <+ zi_nd(I(in),{1},{1},T);
I(out) <+ zi_nd(I(out),{1},{1},T);
 
I(in) <+ G*(V(in1)-V(out2));
I(out) <+ G*(V(out1)-V(in2));
 
end
endmodule

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