umursengul
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I'm just a newbie in Verilog so please be patient :smile:
Ok, here is my problem.
I'm trying to write an 8 bit adder code from the exercise 2 of the chapter 3 of the book Verilog Quickstart (James M. Lee) 2nd Edition.
My code is below:
I'm using ModelSim PE 10.0 Student Edition. And I'm having a error about bit sizes. Here it is:
And I couldn't figure it out!!
Anyone can help?? :-(
Ok, here is my problem.
I'm trying to write an 8 bit adder code from the exercise 2 of the chapter 3 of the book Verilog Quickstart (James M. Lee) 2nd Edition.
My code is below:
Code:
// TEST MODULE //
module test_adder;
reg [7:0] a, b;
reg carry_in ;
wire [7:0] sum;
wire carry_out;
adder8 dut(carry_out, sum, a, b, carry_in);
initial begin
a = 0; b = 0; carry_in = 0;
# 100 if (sum !== 0) begin
$display("sum is wrong" );
$finish;
end
a = 1; b = 0; carry_in = 0;
# 100 if (sum !== 1) begin
$display("sum is wrong") ;
$finish;
end
a = 0; b = 0; carry_in = 1;
# 100 if (sum !== 1) begin
$display("sum is wrong" );
$finish;
end
a = 5; b = 6; carry_in = 1;
# 100 if (sum !== 12) begin
$display("sum is wrong" );
$finish;
end
a = 200; b = 55; carry_in = 1;
# 100 if (sum !== 0) begin
$display("sum is wrong") ;
$finish;
end
a = 18; b = 200; carry_in = 1;
# 100 if (sum !== 219) begin
$display("sum is wrong" );
$finish;
end
$finish ;
end
endmodule
// ADDER MODULE //
module adder(A, B, Cin, Cout, SUM);
input A, B;
input Cin;
output Cout, SUM;
wire half_carry_ab, half_sum, half_carry_cin;
and I1(half_carry_ab, A, B);
xor I3(half_sum, A, B);
and I2(half_carry_cin, Cin, half_sum);
xor I4(SUM, Cin, half_sum);
or I5(Cout, half_carry_cin, half_carry_ab);
endmodule
// 2 BIT ADDER MODULE //
module adder2(A, B, Cin, Cout, SUM);
input [1:0] A, B;
input Cin;
output [1:0] SUM;
output Cout;
wire internal_carry;
adder hi(Cout, SUM[1], A[1], B[1], internal_carry);
adder lo(internal_carry, SUM[0], A[0], B[0], Cin);
endmodule
// 4 BIT ADDER MODULE //
module adder4(A, B, Cin, Cout, SUM);
input [3:0] A, B;
input Cin;
output [3:0] SUM;
output Cout;
wire internal_carry;
adder2 hi(Cout, SUM[3:2], A[3:2], B[3:2], internal_carry);
adder2 lo(internal_carry, SUM[1:0], A[1:0], B[1:0], Cin);
endmodule
// 8 BIT ADDER MODULE //
module adder8(A, B, Cin, Cout, SUM);
input[7:0] A, B;
input Cin;
output [7:0] SUM;
output Cout;
wire internal_carry;
adder4 hi(Cout, SUM[7:4], A[7:4], B[7:4], internal_carry);
adder4 lo(internal_carry, SUM[3:0], A[3:0], B[3:0], Cin);
endmoduleI'm using ModelSim PE 10.0 Student Edition. And I'm having a error about bit sizes. Here it is:
Code:
# vsim work.test_adder
# Loading work.test_adder
# Loading work.adder8
# Loading work.adder4
# Loading work.adder2
# Loading work.adder
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# File in use by: Hostname: ProcessID: 1
# Attempting to use alternate WLF file "./wlftrz371y".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# Using alternate file: ./wlftrz371y
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(53).
# Region: /test_adder/dut
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(53).
# Region: /test_adder/dut
# ** Error: (vsim-3053) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): Illegal output or inout port connection for "port 'Cout'".
# Region: /test_adder/dut
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(53).
# Region: /test_adder/dut
# ** Error: (vsim-3053) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): Illegal output or inout port connection for "port 'SUM'".
# Region: /test_adder/dut
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(8): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(53).
# Region: /test_adder/dut
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(60): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(60): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(60): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(60): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/hi/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(61): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(61): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(61): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(61): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(66).
# Region: /test_adder/dut/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(74): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/hi
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'A'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cin'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'Cout'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/lo
# ** Warning: (vsim-3015) C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(75): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'SUM'. The port definition is at: C:/Users/User/Documents/[4] COURSES_LEARNING/BIL466_EmbeddedSystems/Code_Tryouts/eightBitHierarchicalAdder.v(80).
# Region: /test_adder/dut/lo/lo
# Error loading design
quit -sim
verror 3015
#
# vsim Message # 3015:
# The size in bits of an object connected to a port must match the size
# in bits of the port or the size in bits of the port multiplied by the
# number of module instances. The first number given for the port size is
# the size in bits of the port. The second number given for the port size
# is the size in bits of the port multiplied by the number of module
# instances. Here is an example of code that causes this warning to occur:
#
# module bottom(i1, o1);
# input i1;
# output o1;
# wire [0:4] i1;
# wire [0:4] o1;
# assign o1 = i1;
# endmodule
#
# module top;
# reg [4:0] r1;
# wire [1:0] w1;
# bottom b1 (r1,w1);
# initial begin
# $monitor("w1 = %b", w1);
# #10 r1 = 'b00000;
# #10 r1 = 'b00011;
# #10 r1 = 'b00001;
# end
# endmodule
#
# Note that port 'o1' is 5 bits wide whereas wire 'w1' is only 2 bits wide.
# This message is controlled by the vsim option +nowarnPCDPC.
#And I couldn't figure it out!!
Anyone can help?? :-(
