Verilog: 8-bit Adder Error: The logic does not match a known FF or Latch template

Valerius said:

As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:

Code:

module Addr_8bit(Clk, Rst, En, LEDOut  
    );

     input Clk;
     input Rst;
     input En;
     output reg [7:0] LEDOut;

    always @(posedge Clk or posedge Rst) begin
            if(Rst)
                LEDOut <= 8'b00000000;
            if(En)
                LEDOut <= LEDOut + 8'b00000001;
    end
endmodule

The error is on the line where the non-blocking assignment:

Code:

LEDOut <= LEDOut + 8'b00000001;

is located.

Particularly it says that:

Code:

ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).

Thank You.

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