Verification of an FPGA project that includes Microblaze soft core

I am trying to use SystemVerilog with Active-HDL tools to verify a project that includes Xilinx microblaze soft core. The project includes a software (in C) that is developed in Xilinx SDK tool.
How can I include this software part (the code that is developed for microblaze in Xilinx SDK tool) in my SystemVerilog simulations?

I'm not sure you really want to run the microblaze in your simulation. Just to boot the microblaze will take hundreds of microseconds if not hundreds of milliseconds of simulation time. If you really want to do this you'll have to load the mif files into block rams and also initialize any external ram that you are using (if any, unless that is managed by the by the boot sequence).

Last time I used a processor core in an FPGA we created bus functional model that just emulated the functionality of the software running on the processor.

Regards

Thank you for your help. I was wondering if you can provide more information on how you created and used the bus functional model. I am trying to make sure that I am in right path...

I googled it, I found a document from Xilinx that suggests using "Create/Import User Peripheral" (in XPS) to develop BFM simulation, which helps to create a new EDK IP. But I am not sure that the IP generated includes the software developed in SDK.

Thank you again for your time..

Basically we developed a model of the processor interfaces and the transactions it would perform in the system.

In our case the processor was in the datapath and performed a timing correction function. The hardware would extract timing information and send these to the embedded uC through a memory mapped interface. The model would perform the bus transactions to read the memory and do a simple calculation on the data and write the new data to output memory mapped interface. As the uC wasn't doing any kind of control function it was relatively easy to build a model of it.

For any kind of control uC I would likely create a much more complex BFM that would use pseudo-code to emulate the actual embedded code, but would be transaction based. So say setting some FPGA register from the uC would really just be a bus transaction being performed from the testbench.

Regards

Not sure if i got your problem correctly, but you can create your simulation testbench and multiple DO file by using XPS(xilinx platform studio).
You can convert those files and scripts for Active-HDL.