Verification IP (VIP)

Status
Not open for further replies.
V

vinayssskadam

Newbie level 1
Joined
Nov 26, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
10
What is Verification IP in VLSI? How to use it for verification ?
 

Hello Vinay,

VIP is the verified IP(it can be either testbench or RTL). Anyway you just need to integrate them to our testbench. Specification/documentation will be provided with every VIP which helps you to understand the usage of the same.
 

What is synthesizable Verification IP (examples?) ?
 

As the name suggests, a VIP built using synthesizable RTL (VHDl, Verilog, SV) constructs, which can be realized on silicon.
 

synthesizable VIP (or accelerated VIP as some vendors call it) are IPs that can be synthesized into emulators/FPGA to support verification. Advantage of using them is you can provide real time test stimulus to your synthesized design in FPAG/ASIC.

You can search accelerated VIP and you can find many examples of the same.
Hope this helps.
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…