verification in vhdl/verilog

[lucky_2]

hello,

Can any body provide me the study material regarding the verification in vhdl/verilog

waiting for response

 

[vvvvv]

try search in EDA Ebook upload download forum for
verification, there a lot of free points book for download

 

[the_penetrator]

Well,

the most organized attempt to verification constructs in pure VHDL/Verilog is the OVL library:
https://www.accellera.org

However, it seems that accellera has chosen not to promote the VHDL implementation but only the SystemVerilog OVL. I believe it is not expected to see any revision on the VHDL OVL implementation (dates back to 2003).

cheers

the_penetrator©

 

[kumar_eee]

If u got any material,plz send me a copy of it...