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Verification coverage of the inter signal between blocks inside DUT

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hongzeng

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I want to check some signals of the interface between two block: let's say Pre-processor and a ALU. Are there any direct way to check these signals so I can prevent the bugs of the first stage to affect the second one.
Should I use another receiver and checker to keep this verification environment reusable?
Thank you!
 

Great a packet to store these signals?
 

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