Verification by Non-HDL(C++/Java)??

[davyzhu]

Hi all,

I found that some verification procedure using Non-HDL such as C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

 

[aji_vlsi]

Hi all,

I found that some verification procedure using Non-HDL such as C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

Hi Davy,
Take a look at TEAL http://teal.sf.net for one such approach. I would however recommend you to look at SystemVerilog instead.

Regards
Ajeetha, CVC
www.noveldv.com

 

[davyzhu]

Hi Ajeetha,

Thank you

I have take a look at TEAL and wish to gain some idea.

Does SystemVerilog use some techniques other than PLI?

Best regards,
Davy

 

[aji_vlsi]

Hi Ajeetha,

Does SystemVerilog use some techniques other than PLI?

Best regards,
Davy

Lots and lots... read SV LRM or my SNUG 06 paper for some references.

Ajeetha, CVC
www.noveldv.com

 

[maxsnail]

when two language cosimulation, the communication is through systemcall,and VPI,
delay or posedge can be implemnet in both simulator

 

[omara007]

You need to check things like SystemC, E, and Vera ..
You can also try tools like ModelSim or CCSS to verify an HDL block using SystemC for example ..